DDR3 SDRAM pins are shuffeled?

[yekta]

Hi,

In the schematics of one of the reference design four 2G_DDR3 (128x16) chips are used.

I realised that the DQ0-DQ15 pins are not connected to the DRAM_D0-DRAM_D15 Bus and
DRAM_D16-DRAM_D31 Bus in the numerical order.

High Byte Pins are shuffeled and Low byte pins are shuffeled .

I suppose these pins are swapped to be able to make the layout connections easily.

What do you think?

[Yuri]

Some additional restrictions may relate to write leveling calibration, when it may be needed
the following : 

- DQ0 of DDR3 device is connected with D0 of i.MX53 ESDCTL ;

- DQ8 of DDR3 device is connected with D8 of i.MX53 ESDCTL ;

- DQ16 of DDR3 device is connected with D16 of i.MX53 ESDCTL ;

- DQ24 of DDR3 device is connected with D24 of i.MX53 ESDCTL.

 In the same time this may be not the problem, because of the next points :

 1.

Write leveling is associated with the DDR fly-by board topology.

If such topology is not applied - no need for write leveling.

2.

DRAM may have the option to drive leveling feedback on a prime DQ or all DQs. 

[NitinSonar]

Hi,

I have designed custom board based on these connection shuffling and works well. The two rules mention hold absolutely true. You can follow pin shuffel similar to SABER AUTO which works.

Best Regards

Nitin Sonar

[ronak123]

Yes, It is. It is called data swapping.

Remember 2 rules:

1. Data pins can be swapped within each byte only.

2. DQMx and DQSx must follow receptive byte.

Regards,

Ronak.

[yekta]

OK.

Thanks for the replay.

[Yuri]

From i.MX53 reference design(s) :

NOTE:
DDR data pins can be swapped for improved
routing according to the following rules:

1) Data pins can be swapped within each byte

2) Data bytes can be swapped

3) DQMx and DQSx must follow each byte
When swapping bytes 0 or 1 into 2 or 3, must then use
32 bit access. Cannot use 16-bit access.