DDR3 RAM configuration on NXP i.MX6UL evk

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DDR3 RAM configuration on NXP i.MX6UL evk

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embedded_Dev
Contributor III

Hello everyone,

I am using NXP i.MX6UL evk and i want to configure the DDR3L RAM for customized board based on NXP i.MX6UL evk. I used the  RPA tool , ddr test and uboot dcd header. My new RAM is having 2133Mbps data rate of 4GB capacity (256Mwords X 16bits) . Row Address =15

Column address =10 .  When i fill 1066 and 2133 as Clock Cycle Frequencies(MHz) , it is showing error and when i use 400, then the error is resolved. Can you please check this issue. For stress test, where do we get scripts for testing? They are more defconfig files in uboot regarding imx6ul evk nxp board. Which defconfig should i use for DDR3 RAM ?

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi

 

>When i fill 1066 and 2133 as Clock Cycle Frequencies(MHz) , it is showing error and
>when i use 400, then the error is resolved.

400 is correct as max. operating frequency of MMDC controller is 400MHz.

 

> For stress test, where do we get scripts for testing?

please look at below presentation p.22, 29 for script usage

https://community.nxp.com/t5/NXP-FTF-2016-Training/DES-N1936-i-MX-6UltraLite-DDR-Tools-Overview-and-...

 

>Which defconfig should i use for DDR3 RAM ?

one can use imx6ul evk defconfig file.

 

Best regards
igor

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embedded_Dev
Contributor III

Hi ,

I have tested the callibration and stress tests. I filled the values from the callibration test in imximage.cfg.

I compiled the u-boot and i filled the values in board/freescale/mx6ul_14x14_evk/imximage.cfg

The following are the values from the files imximage.cfg

----------------------------------------------------------------------------------------

/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/

#define __ASSEMBLY__
#include <config.h>

/* image version */

IMAGE_VERSION 2

/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/

#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#elif defined(CONFIG_NOR_BOOT)
BOOT_FROM nor
#else
BOOT_FROM sd
#endif

#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000
#else

#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif

/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Boot configuration */
DATA 4 0x020d8004 0x00000872
DATA 4 0x020d801c 0x01000041

/* DDR type MT41K256M16HA-125 which is EOL */

/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff

#ifdef CONFIG_IMX_OPTEE
DATA 4 0x20e4024 0x00000001
CHECK_BITS_SET 4 0x20e4024 0x1
#endif

DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000

/*CLOCK */
DATA 4 0x020E027C 0x00000030

/* CONTROL AND ADDRESS */
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x000C0030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030

/* DATA STROBES */
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030

/* DATA */
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030

DATA 4 0x021B001C 0x00008000

/* CALIBRATIONS */
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x00000000
DATA 4 0x021B083C 0x415C015C
DATA 4 0x021b0840 0x00000000
DATA 4 0x021B0848 0x40405052
DATA 4 0x021B0850 0x40405046

DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333

DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333

DATA 4 0x021B08C0 0x00921012

DATA 4 0x021B08B8 0x00000800

/* MMDC INIT */
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333030
DATA 4 0x021B000C 0x676B52F3
DATA 4 0x021B0010 0xB64D0B63
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00201740
DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000004F
DATA 4 0x021B0000 0x84180000

DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x15208030
DATA 4 0x021B001C 0x04008040

DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002556D
DATA 4 0x021B0404 0x00011066
DATA 4 0x021B001C 0x00000000
#endif

 

------------------------------------------------------------------------------------------------------

 

But when i am trying the flash the image, i am getting the following error .

ERROR : Cannot find valid IVT header

Thanks...................

 

 

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