Hello,
There is no need for DDR3 ODT pulling down.
DDR3 DRAM_RESET should be pulled down to meet the JEDEC sequence until the controller is
configured and starts driving. DRAM_RESET should be kept high when DDR3 enters self-refresh mode.
DDR3 SDCKE[1:0] pull-down is used in the SDP\B, although it is not recommended.
DRAM_SDCKE0 and DRAM_SDCKE1 require external resistors (such as 10 kΩ) to GND to minimize current
drain during deep sleep mode (DSM).
The BSP (Board Support Package) uses a common DDR routine for both fly-by and T-topology designs.
Fly-by designs have parallel resistor termination on address lines, while T-topology does not.
During low-power self refresh, the BSP programs pad control register GRP_CTLDS to 0x00000000. Therefore,
DRAM_SDCKE0, DRAM_SDCKE1, and other associated GRP_CTLDS I/O are forced to the high-impedance state.
Because DRAM_SDCKE0 and DRAM_SDCKE1 are forced to high-Z, external pull-down resistors are required to
avoid floating outputs during standby.
Have a great day,
Yuri
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