DDR2 HW ZQ Calibration

[yekta]

Hi Community Members

I checked the DRAM_SDCKL_P and DRAM_SDCLK_N  signals in my HW ( no u-boot prompt) ,
the DC level of these signals should be VDDQ/2=Vref=0.9V , but I measured about 1.25Vdc.

Then I found an application note AN4466:imx53 DDR Calibration .Which says:

"Altough ODT activation is not typical for DDR2 ,it should be noted that ZQ calibration is recommended for setting the right bias for the DDR2 signals"

On another page : "Calibration sequence should be executed after the DDR memory has been initialized."

The DDR init code is in flash_header.S .
 I have to start the calibration by setting a bit of the ZQ ESDCTL register and wait until HW clears this bit(calibration done).

I dont know how to add this into flash_header.S.

Does  anybody know  any board example which uses DDR Calibration sequence ?
Or does anybody want to share his/her solution?

[Yuri]

You are right :
According to section 3.1 (DDR2) of app note AN4466 “i.MX53 DDR Calibration” :

Although ODT activation is not typical for DDR2, it should be noted that the ZQ
calibration is recommended for setting the right VCC/2 bias for the DDR2 signals.

   Also, with the ZQ calibration, the drive strength can be calibrated too.

Please look at the next command from the enclosed DDR2 init script :

// Enable ZQ calibration to tightly control the impedance of the DDR IO pads

setmem /32 0x63fd9040 = 0x04b80003 // keep ZQ HW control values and enable it

The script may be used as an DDR2 init example.

[HitoshiOgasawar]

The information, thank you.
Because it is weak at English, it is being delayed by the understanding.
Thank you.