DDR reserved bits cleared during boot

[pavelstanek]

Hello,

I have small question about reserved bits in DDR subsystem.

Let's use i.MX6Q sabre board (mx6qsabresd) , and nearly any Linux SDK.

Let's picup some register, for example IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 (0x020e059c), but there are others with same problem.

In documentation there is that reset value is 0x00003030

In U-boot there are records in *.cfg files (for device configuration block - ROM init) like

DATA 4, 0x020e059c, 0x00000030

So this will set DSE value of pin, but also clears reserved bits (bits 15-12) during ddr init by rom code.

Is it correct to clear these reserved bits? Are they useful for anything?

And is it safe to clear them?

[Yuri · Accepted solution]

Hello,

The reserved bits concern with preliminary i.MX6 specs, where PUE and PKE
bits were used (to define pull up options). Strictly speaking, initialization code should

follow recent RM recommendations.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------