DDR calibration values for mass production

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DDR calibration values for mass production

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papanastasiou
Contributor I

we have a custom board with DDR3 and IMX6Q and we would like to generate a calibration file for mass production according to the instructions of the attached pdf document. we will use 10 boards running DDR calibration in both 25C and 40C. since the calculations we have to do are too much, is there a tool we can enter our data and get the values for the calibration registers?

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Yuri
NXP Employee
NXP Employee

@papanastasiou 
Hello,

  if memory returns all bits in byte, but not only the LSB - no problem.
Please consult with memory manufacturer.

 

Regards,
Yuri.

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papanastasiou
Contributor I

Hello,

we have a board and for bytes 2 and 4 the LSB is not connected by mistake to the LSB DQ pins of the DDR ICs. I would like to ask if the calibration file we generate is valid and if the system will be stable

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Yuri
NXP Employee
NXP Employee

@papanastasiou 
Hello,

  if memory returns all bits in byte, but not only the LSB - no problem.
Please consult with memory manufacturer.

 

Regards,
Yuri.

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Yuri
NXP Employee
NXP Employee

@papanastasiou 
Hello,

   We do not have special tool to select proper mean values. The approaches,
described in the presentation, are quite reasonable. 

Regards,
Yuri.

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papanastasiou
Contributor I

thank you for your reply. I just have one question concerning DDR connections, we have to follow the rule the low order bit of each byte must reside at bit 0 of the byte, correct? the remaining 7 data bits can be swapped freely, correct? otherwise DDR calibration fails, correct? I am attaching a part of a schematic with one DDR IC, can you confirm that byte 2 is wrong? since the LSB bit of the byte 2 is not connected at DQ0 of the DDR IC

ddr.jpg

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Yuri
NXP Employee
NXP Employee

@papanastasiou 
Hello,

  generally  this is correct - just the LSB (Least Significant Bit) is used for the write leveling:
"i.MX6  repeatedly sends single strobes on DQSx. DDR continuously samples CK on DQSx rising edge and feeds back the result to DQx LSB bit. When CK and DQSx are unaligned, the returned value is ‘0.’ i.MX6 then adds delay to DQSx, until ‘1’ is returned on DQx LSB bit.

  But You may consult with memory provider - if DDR returns '1' for all bits in the byte. 

Regards,
Yuri.

 

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