DDR calibration on Imx6

[dhanunjay]

Dear Team,

I wanted to test DDR calibration on imx6. Testing only for Write leveling, DQS, Read/write leveling.

DDR start address s 0X10000000 DDR size 2GB.

in this DDR3 allocations :

cached ram size is : DDR base addr + 2GB - 1MB

uncached ram is : last 1MB

pagetable is placed at end of the cached ram.

when running  the DDR calibration tests, I got the following error.

=============================STARTING DDR CALIBRATION=============================

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x002C001F

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x002C002A

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00240033

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x0016002A

Starting DQS gating calibration...

**Memory did not transfer correctly, DDRtest_SSN_memcpy2 failed

...

We are using 64-bit DDR3 memory, here we observe that CSD0_base_address and some other variable content is lost/overwriting with some garbage value. while executing the tests.

Can you please suggest the problem solution.

[dhanunjay · Accepted solution]

Hi ALL,

I have changed some of the drive strength parameters in DDR config code, all tests are passing.

But I configured Write levelling parameters as:

     0x021b080c =     0x001F001F   

     0x021b0810 =     0x001F001F   

     0x021b480c =     0x001F001F   

     0x021b4810 =     0x001F001F

and output values are:

Start write leveling calibration

Write leveling calibration completed

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x004E0051

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00420048

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00330031

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x0030003F

could please help me, the output values are larger than configured values?

Do i need to change any configuration parameters.

Please suggest me.

[igorpadykov]

Hi DHANUNJAY

If the value of any of the WL_DL_ABS_OFFSETn [MPWLDECTRL0] register fields

are greater than ‘1F’, WALAT should be set to ‘1’ .

WALAT should be further increased for any full cycle delays added by the

WL_CYC_DELn register fields.

For "SSN_memcpy2" error recommended to test memory with lower ddr/cpu

frequencies, as this may be caused by board noise.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[dhanunjay]

Hi igor,

Greetings!

Thanks for very quick response!!

After changing WALT to 1 and write 0x021b0018 = 0x00011740

Then also same issue is repeating:

=============================STARTING DDR CALIBRATION=============================

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x002A001F

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x002C0028

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00250031

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x00140029

Starting DQS gating calibration...

**Memory did not transfer correctly, DDRtest_SSN_memcpy1 failed

**Memory did not transfer correctly, DDRtest_SSN_memcpy2 failed

. . .

Any other inputs?

[dhanunjay]

We are running CPu at 600Mhz

and DDR3 @ 400Mhz.

[igorpadykov]

Hi DHANUNJAY

one can tweak drive strength settings, this may be done

both on i.MX6 and DDR side.

~igor

[dhanunjay]

Hi Igor,

Greetings!!

I tried with all combinations/drive parameters but no luck.

I observed, while executing  ddr_calibration_sw( 0x00,0x02); It prforms internally memcpy() op, the (CSD0_BASE_ADDRESS=0x10000000) variable value becomes zero.how it is possible, the DDR testcode in IRAM.

How this value becomes zero?

If i declare macro, it will throwing errors like **Memory did not transfer correctly, DDRtest_SSN_memcpy2 failed.

Please give your suggestion on this.

Thanks,

Dhanunjay

[igorpadykov]

Hi Dhanujay

test should show info like:

Address of test2 failure:   Data was:

But pattern was:

based on that one can check fault bits (pattern) with oscilloscope.

Further one can slow down ddr frequency.

If this will not help, attach jtag and write the same pattern with jtag,

again controlling waveforms with oscilloscope.

Best regards

igor

[dhanunjay]

Hi,

Here is log:

Data was: 0xE59FF01CE59FF01C

But pattern was: 0xAAAAAAAAAAAAAAAA

Source is wrong, it is:   0x02C6D7E600000450

Address ÿË

á55)éÁáÁÁåÅÝÕÉ

write leveling is passed, but ddr_calibration_sw() failed.