DDR Stress Test is not completing for LPDDR2

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DDR Stress Test is not completing for LPDDR2

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srinivasaporam
Contributor II

Hi,

We have got Freescale IMX6D processor board with which we are using LPDDR2 (32 bit). Now , we are running DDR Stess Tester which is happening till some time and then stucking at that point.

******************************

    DDR Stress Test (1.0.3) for MX6DQ

    Build: Jun 25 2014, 12:09:21

    Freescale Semiconductor, Inc.

******************************

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is LPDDR2 in 1-channel mode.

Data width: 32, bank num: 8

Row size: 14, col size: 9

Chip select CSD0 is used

Density per chip select: 256MB

==================================

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz

  ARM set to 1.2GHz

Please select the DDR density per CHANNEL (in bytes) on the board

Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6

for 32MB

Note, if there are two chip selects per channel, then input the combined densit

y of

  both chip selects per channel

  DDR density selected (MB): 256

  CHANNEL0 is selected.

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.

If you want to run at other DDR frequency. Type 'n'

  DDR Freq: 528 MHz

Would you like to run the read/write calibration? (y/n)

Note: Array result[] holds the DRAM test result of each byte.

      0: test pass.  1: test fail

      4 bits respresent the result of 1 byte.

      result 0001:byte 0 fail.

      result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000   result[00]=0x1111

ABS_OFFSET=0x04040404   result[01]=0x1111

ABS_OFFSET=0x08080808   result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C   result[03]=0x1111

ABS_OFFSET=0x10101010   result[04]=0x1111

ABS_OFFSET=0x14141414   result[05]=0x1111

ABS_OFFSET=0x18181818   result[06]=0x1111

ABS_OFFSET=0x1C1C1C1C   result[07]=0x1111

ABS_OFFSET=0x20202020   result[08]=0x1111

ABS_OFFSET=0x24242424   result[09]=0x1111

ABS_OFFSET=0x28282828   result[0A]=0x1111

ABS_OFFSET=0x2C2C2C2C   result[0B]=0x1111

after this it is not progressing any more. We have waited for 1hr to 2hrs also.

I have some queries like:

1.  Why is Density per chip select: 256MB ??? when we are using 2G LPDDR2 with single channel and Single Die and 1 chip select. Our LPDDR2 part number is MT42L64M32D1TK-18 IT:C from Micron Technology.

I have attached LPDDR2 Script aid which i have edited for our part number and Data sheet for LPDDR2 (MT42L64M32D1TK-18 IT:C)

Any help in this regard is appreciated

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srinivasaporam
Contributor II

Hi,

Iam running DDR Stress like this:

Microsoft Windows [Version 6.1.7601]

Copyright (c) 2009 Microsoft Corporation.  All rights reserved.

C:\Users\srinivasa\Desktop\DDR_Stress_Tester_V1.0.3\Binary>DDR_Stress_Tester.exe

-t mx6x -df LPDDR2.inc

where as LPDDR2.inc is as follows:

//=============================================================================
//init script for i.Mx6Q LPDDR2
//=============================================================================
// Revision History
// v01
//=============================================================================
wait = on
//=============================================================================
// DisableWDOG
//=============================================================================
//setmem /160x020bc000 =0x30
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
setmem /320x020c4068 =0xffffffff
setmem /320x020c406c =0xffffffff
setmem /320x020c4070 =0xffffffff
setmem /320x020c4074 =0xffffffff
setmem /320x020c4078 =0xffffffff
setmem /320x020c407c =0xffffffff
setmem /320x020c4080 =0xffffffff
setmem /320x020c4084 =0xffffffff
//setmem /320x020c4018 =0x00060324//DDR clk to 400MHz
// Switch PL301_FAST2 to DDR Dual-channel mapping
//setmem /320x00B00000 =0x1
//=============================================================================
// IOMUX
//=============================================================================
//DDR IO TYPE:
setmem /320x020e0798 =0x00080000// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
setmem /320x020e0758 =0x00000000// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
setmem /320x020e0588 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
setmem /320x020e0594 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//ADDRESS:
setmem /320x020e056c =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
setmem /320x020e0578 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
setmem /320x020e074c =0x00000038// IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
setmem /320x020e057c =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
setmem /320x020e058c =0x00000000// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
setmem /320x020e059c =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
setmem /320x020e05a0 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
setmem /320x020e078c =0x00000038// IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
setmem /320x020e0750 =0x00020000// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
setmem /320x020e05a8 =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
setmem /320x020e05b0 =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
setmem /320x020e0524 =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
setmem /320x020e051c =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
//setmem /320x020e0518 =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
//setmem /320x020e050c =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
//setmem /320x020e05b8 =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
//setmem /320x020e05c0 =0x00003038// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
//Data:
setmem /320x020e0774 =0x00020000// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
setmem /320x020e0784 =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B0DS
setmem /320x020e0788 =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B1DS
setmem /320x020e0794 =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B2DS
setmem /320x020e079c =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B3DS
//setmem /320x020e07a0 =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B4DS
//setmem /320x020e07a4 =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B5DS
//setmem /320x020e07a8 =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B6DS
//setmem /320x020e0748 =0x00000038// IOMUXC_SW_PAD_CTL_GRP_B7DS
setmem /320x020e05ac =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
setmem /320x020e05b4 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
setmem /320x020e0528 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
setmem /320x020e0520 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
//setmem /320x020e0514 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
//setmem /320x020e0510 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
//setmem /320x020e05bc =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
//setmem /320x020e05c4 =0x00000038// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer:Micron
// Device Part Number:MT42L64M32D1TK-18 IT:C
// Clock Freq.:528MHz
// MMDC channels:MMDC0
// Density per CS in Gb:2
// Chip Selects used:1
// Number of Banks:8
// Row address:    14
// Column address:9
// Data bus width32
//=============================================================================
setmem /320x021b001c =0x00008000// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
//setmem /320x021b401c =0x00008000// MMDC1_MDSCR, set the Configuration request bit during MMDC set up
setmem /320x021b085c =0x1B5F0107//MMDC0_MPZQLP2CTL,LPDDR2 ZQ params
//setmem /320x021b485c =0x1B5F0107//MMDC1_MPZQLP2CTL,LPDDR2 ZQ params
//=============================================================================
// Calibration setup.
//=============================================================================
setmem /320x021b0800 =0xA1390003// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
//ca bus abs delay
setmem /320x021b0890  =0x00400000// values of 20,40,50,60,7f tried. no difference seen
//setmem /320x021b4890 =0x00400000// values of 20,40,50,60,7f tried. no difference seen
//Read calibration
setmem /320x021b0848 =0x40404040// MPRDDLCTL PHY0
//setmem /320x021b4848 =0x40404040// MPRDDLCTL PHY1
//Write calibration                   
setmem /320x021b0850 =0x40404040// MPWRDLCTL PHY0
//setmem /320x021b4850 =0x40404040// MPWRDLCTL PHY1
//dqs gating dis
setmem /320x021b083c =0x20000000
setmem /320x021b0840 =0x00000000
//setmem /320x021b483c =0x20000000
//setmem /320x021b4840 =0x00000000
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
setmem /320x021b081c =0x33333333// DDR_PHY_P0_MPREDQBY0DL3
setmem /320x021b0820 =0x33333333// DDR_PHY_P0_MPREDQBY1DL3
setmem /320x021b0824 =0x33333333// DDR_PHY_P0_MPREDQBY2DL3
setmem /320x021b0828 =0x33333333// DDR_PHY_P0_MPREDQBY3DL3
//setmem /320x021b481c =0x33333333// DDR_PHY_P1_MPREDQBY0DL3
//setmem /320x021b4820 =0x33333333// DDR_PHY_P1_MPREDQBY1DL3
//setmem /320x021b4824 =0x33333333// DDR_PHY_P1_MPREDQBY2DL3
//setmem /320x021b4828 =0x33333333// DDR_PHY_P1_MPREDQBY3DL3
//write data bit delay: (3 is the reccommended default value, although out of reset value is 0)
setmem /320x021b082c =0xF3333333// DDR_PHY_P0_MPREDQBY0DL3
setmem /320x021b0830 =0xF3333333// DDR_PHY_P0_MPREDQBY1DL3
setmem /320x021b0834 =0xF3333333// DDR_PHY_P0_MPREDQBY2DL3
setmem /320x021b0838 =0xF3333333// DDR_PHY_P0_MPREDQBY3DL3
//setmem /320x021b482c =0xF3333333// DDR_PHY_P1_MPREDQBY0DL3
//setmem /320x021b4830 =0xF3333333// DDR_PHY_P1_MPREDQBY1DL3
//setmem /320x021b4834 =0xF3333333// DDR_PHY_P1_MPREDQBY2DL3
//setmem /320x021b4838 =0xF3333333// DDR_PHY_P1_MPREDQBY3DL3
//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
//setmem /320x021b08c0 =0x24911492// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
//setmem /320x021b48c0 =0x24911492
// Complete calibration by forced measurement:                 
setmem /320x021b08b8 =0x00000800// DDR_PHY_P0_MPMUR0, frc_msr
//setmem /320x021b48b8 =0x00000800// DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================
// Channel0 - startng address 0x80000000
setmem /320x021b0004 =0x00020036// MMDC0_MDPDC
setmem /320x021b0008 =0x00000000// MMDC0_MDOTC
setmem /320x021b000c =0x444961A5// MMDC0_MDCFG0
setmem /320x021b0010 =0x00160E83// MMDC0_MDCFG1
setmem /320x021b0014 =0x000000DD// MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
setmem /320x021b0018 =0x00001748// MMDC0_MDMISC
setmem /320x021b001c =0x00008000// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
setmem /320x021b002c =0x149F26D2// MMDC0_MDRWD
setmem /320x021b0030 =0x00000010// MMDC0_MDOR
setmem /320x021b0038 =0x0021099B// MMDC0_MDCFG3LP
setmem /320x021b0040 =0x0000000F// Chan0 CS0_END
setmem /320x021b0400 =0x11420000// MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
setmem /320x021b0000 =0x83010000// MMDC0_MDCTL
// Channel1 - starting address 0x10000000
//setmem /320x021b4004 =0x00020036// MMDC1_MDPDC
//setmem /320x021b4008 =0x00000000// MMDC1_MDOTC
//setmem /320x021b400c =0x444961A5// MMDC1_MDCFG0
//setmem /320x021b4010 =0x00160E83// MMDC1_MDCFG1
//setmem /320x021b4014 =0x000000DD// MMDC1_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
//setmem /320x021b4018 =0x00001748// MMDC1_MDMISC
//setmem /320x021b401c =0x00008000// MMDC1_MDSCR, set the Configuration request bit during MMDC set up
//setmem /320x021b402c =0x149F26D2// MMDC1_MDRWD
//setmem /320x021b4030 =0x00000010// MMDC1_MDOR
//setmem /320x021b4038 =0x0021099B// MMDC1_MDCFG3LP
//setmem /320x021b4040 =0x0000000F// Chan1 CS0_END
//setmem /320x021b4400 =0x11420000// MMDC1_MAARCR ADOPT optimized priorities. Dyn jump disabled
//setmem /320x021b4000 =0x83010000// MMDC1_MDCTL
// Channel0 : Configure DDR device:     
//CS0
setmem /320x021b001c =0x003F8030// MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0
setmem /320x021b001c =0xFF0A8030// MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff
setmem /320x021b001c =0xC2018030// MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2
setmem /320x021b001c =0x06028030// MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
setmem /320x021b001c =0x01038030// MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6
//CS1
//setmem /320x021b001c =0x003F8038// MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0
//setmem /320x021b001c =0xFF0A8038// MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff
//setmem /320x021b001c =0xC2018038// MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2
//setmem /320x021b001c =0x06028038// MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
//setmem /320x021b001c =0x01038038// MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6
// Channel1 : Configure DDR device:     
//CS0
//setmem /320x021b401c =0x003F8030// MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0
//setmem /320x021b401c =0xFF0A8030// MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff
//setmem /320x021b401c =0xC2018030// MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2
//setmem /320x021b401c =0x06028030// MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
//setmem /320x021b401c =0x01038030// MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6
//CS1
//setmem /320x021b401c =0x003F8038// MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0
//setmem /320x021b401c =0xFF0A8038// MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff
//setmem /320x021b401c =0xC2018038// MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2
//setmem /320x021b401c =0x06028038// MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4
//setmem /320x021b401c =0x01038038// MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6
setmem /320x021b0800 =0xA1390003// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
setmem /320x021b0020 =0x00001800// MMDC0_MDREF
//setmem /320x021b4020 =0x00001800// MMDC1_MDREF
setmem /320x021b0818 =0x00000000// DDR_PHY_P0_MPODTCTRL
//setmem /320x021b4818 =0x00000000// DDR_PHY_P1_MPODTCTRL
setmem /320x021b0004 =0x00025576// MMDC0_MDPDC now SDCTL power down enabled
//setmem /320x021b4004 =0x00025576// MMDC0_MDPDC now SDCTL power down enabled
setmem /320x021b0404 =0x00011006// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
//setmem /320x021b4404 =0x00011006// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
setmem /320x021b001c =0x00000000// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
//setmem /320x021b401c =0x00000000// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
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igorpadykov
NXP TechSupport
NXP TechSupport

what is about read/write patterns with ddr tester ?

Are they passed, any data read/write correctly?

You can do it with jtag, may be useful to look at SDK,

it has simple ddr test.

"MX6_PLATFORM_SDK "

https://community.freescale.com/docs/DOC-94139

~igor

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srinivasaporam
Contributor II

I tried changing DDR configuration settings and build u-boot and copied SD card (Uboot as well as Linux). Iam not seeing any Console messages.

DDR Stress test is failing.

ABS_OFFSET=0x00000000   result[00]=0x1111

ABS_OFFSET=0x04040404   result[01]=0x1111

ABS_OFFSET=0x08080808   result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C   result[03]=0x1111

ABS_OFFSET=0x10101010   result[04]=0x1111

ABS_OFFSET=0x14141414   result[05]=0x1111

ABS_OFFSET=0x18181818   result[06]=0x1111

ABS_OFFSET=0x1C1C1C1C   result[07]=0x1111

ABS_OFFSET=0x20202020   result[08]=0x1111

ABS_OFFSET=0x24242424   result[09]=0x1111

ABS_OFFSET=0x28282828   result[0A]=0x1111

ABS_OFFSET=0x2C2C2C2C   result[0B]=0x1111

ABS_OFFSET=0x30303030   result[0C]=0x1111

ABS_OFFSET=0x34343434   result[0D]=0x1111

ABS_OFFSET=0x38383838   result[0E]=0x1111

ABS_OFFSET=0x3C3C3C3C   result[0F]=0x1111

ABS_OFFSET=0x40404040   result[10]=0x1111

ABS_OFFSET=0x44444444   result[11]=0x1111

ABS_OFFSET=0x48484848   result[12]=0x1111

ABS_OFFSET=0x4C4C4C4C   result[13]=0x1111

ABS_OFFSET=0x50505050   result[14]=0x1111

ABS_OFFSET=0x54545454   result[15]=0x1111

ABS_OFFSET=0x58585858   result[16]=0x1111

ABS_OFFSET=0x5C5C5C5C   result[17]=0x1111

ABS_OFFSET=0x60606060   result[18]=0x1111

ABS_OFFSET=0x64646464   result[19]=0x1111

ABS_OFFSET=0x68686868   result[1A]=0x1111

ABS_OFFSET=0x6C6C6C6C   result[1B]=0x1111

ABS_OFFSET=0x70707070   result[1C]=0x1111

ABS_OFFSET=0x74747474   result[1D]=0x1111

ABS_OFFSET=0x78787878   result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C   result[1F]=0x1111

ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

Is there any other way to validate our subsystems like memory, SD card, USB etc.

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srinivasaporam
Contributor II

Hi,

Can you tell, Whether we need to run DDR Stress test, without porting OS (with u-boot , kernel, rootfs etc) on a fresh board on we need to port OS and then run DDR Stress test. We running on a fresh board which has just came after assembly and with out SD card into it.

it is giving all the values as error as:

Microsoft Windows [Version 6.1.7601]

Copyright (c) 2009 Microsoft Corporation.  All rights reserved.

To run at a static freq, simply set the start freq and end freq to the same valu

e

Would you like to run the DDR Stress Test (y/n)?

Enter desired START freq (135 to 672 MHz), then hit enter.

Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.

533

  The freq you entered was: 533

Enter desired END freq (135 to 672 MHz), then hit enter.

Make sure this is equal to or greater than start freq

533

  The freq you entered was: 533

Beginning stress test

loop: 1

DDR Freq: 532 MHz

t0.1: data is addr test

Address of failure: 0x10000000

Data was: 0xffffffff

But pattern  should match address

^C

C:\Users\srinivasa\Desktop\DDR_Stress_Tester_V1.0.3\Binary>DDR_Stress_Tester.exe

-t mx6x -df LPDDR2.inc

MX6DQ opened.

HAB_TYPE: DEVELOP

Image loading...

download Image to IRAM OK

******************************

    DDR Stress Test (1.0.3) for MX6DQ

    Build: Jun 25 2014, 12:09:21

    Freescale Semiconductor, Inc.

******************************

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is LPDDR2 in 1-channel mode.

Data width: 32, bank num: 8

Row size: 14, col size: 9

Chip select CSD0 is used

Density per chip select: 256MB

==================================

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz

  ARM set to 800MHz

Please select the DDR density per CHANNEL (in bytes) on the board

Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6

for 32MB

Note, if there are two chip selects per channel, then input the combined densit

y of

  both chip selects per channel

  DDR density selected (MB): 256

  CHANNEL0 is selected.

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.

If you want to run at other DDR frequency. Type 'n'

  DDR Freq: 528 MHz

Would you like to run the read/write calibration? (y/n)

Note: Array result[] holds the DRAM test result of each byte.

      0: test pass.  1: test fail

      4 bits respresent the result of 1 byte.

      result 0001:byte 0 fail.

      result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000   result[00]=0x1111

ABS_OFFSET=0x04040404   result[01]=0x1111

ABS_OFFSET=0x08080808   result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C   result[03]=0x1111

ABS_OFFSET=0x10101010   result[04]=0x1111

ABS_OFFSET=0x14141414   result[05]=0x1111

ABS_OFFSET=0x18181818   result[06]=0x1111

ABS_OFFSET=0x1C1C1C1C   result[07]=0x1111

ABS_OFFSET=0x20202020   result[08]=0x1111

ABS_OFFSET=0x24242424   result[09]=0x1111

ABS_OFFSET=0x28282828   result[0A]=0x1111

ABS_OFFSET=0x2C2C2C2C   result[0B]=0x1111

ABS_OFFSET=0x30303030   result[0C]=0x1111

ABS_OFFSET=0x34343434   result[0D]=0x1111

ABS_OFFSET=0x38383838   result[0E]=0x1111

ABS_OFFSET=0x3C3C3C3C   result[0F]=0x1111

ABS_OFFSET=0x40404040   result[10]=0x1111

ABS_OFFSET=0x44444444   result[11]=0x1111

ABS_OFFSET=0x48484848   result[12]=0x1111

ABS_OFFSET=0x4C4C4C4C   result[13]=0x1111

ABS_OFFSET=0x50505050   result[14]=0x1111

ABS_OFFSET=0x54545454   result[15]=0x1111

ABS_OFFSET=0x58585858   result[16]=0x1111

ABS_OFFSET=0x5C5C5C5C   result[17]=0x1111

ABS_OFFSET=0x60606060   result[18]=0x1111

ABS_OFFSET=0x64646464   result[19]=0x1111

ABS_OFFSET=0x68686868   result[1A]=0x1111

ABS_OFFSET=0x6C6C6C6C   result[1B]=0x1111

ABS_OFFSET=0x70707070   result[1C]=0x1111

ABS_OFFSET=0x74747474   result[1D]=0x1111

ABS_OFFSET=0x78787878   result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C   result[1F]=0x1111

ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

The DDR stress test can run with an incrementing frequency or at a static freq

To run at a static freq, simply set the start freq and end freq to the same valu

e

Would you like to run the DDR Stress Test (y/n)?

Enter desired START freq (135 to 672 MHz), then hit enter.

Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.

533

  The freq you entered was: 533

Enter desired END freq (135 to 672 MHz), then hit enter.

Make sure this is equal to or greater than start freq

533

  The freq you entered was: 533

Beginning stress test

loop: 1

DDR Freq: 532 MHz

t0.1: data is addr test

Address of failure: 0x10000000

Data was: 0xffffffff

But pattern  should match address

it is stucking at  this point and not progressing any more.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Srinivasa

almost always new board requires modification ddr settings in uboot.

If you are lucky and board is exact copy of some reference board, then

changes are not needed, one can try to run its Demo images, for freescale

reference boards these are:

Board Support Packages (27)

L3.14.28_1.0.0_iMX6QDLS_BUNDLE (REV L3.14.28_1.0.0)

i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo Linux Binary Demo Files and Linux BSP Documentation

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREBRD&fpsp=1&tab=Design_Tool...

If board differs from some supported reference board, for example  below what is supported by yocto

community release:

"Supported Board List"

FSL Community BSP Release Notes 1.8 documentation

then one needs to modify BSP, removing or adding/changing drivers - this is called

porting OS. Actually it is not possible to say for sure, if it is necessary to modify ddr settings

and run DDR Stress test, until all porting is done and full linux image runs on board,

because some ddr errors can appear only running linux, not revealing in uboot.

~igor

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srinivasaporam
Contributor II

Hi ,

Now we running the test with 800 MHz only. Now test is running but it is giving error "

ERROR FOUND, we can't get suitable value !!!! dram test fails for all values. "

Please check the Command Prompt output.

C:\Users\srinivasa\Desktop\DDR_Stress_Tester_V1.0.3\Binary>DDR_Stress_Tester.exe

-t mx6x -df LPDDR2.inc

MX6DQ opened.

HAB_TYPE: DEVELOP

Image loading...

download Image to IRAM OK

Re-open MX6x device.

Running DDR test..., press "ESC" key to exit.

******************************

    DDR Stress Test (1.0.3) for MX6DQ

    Build: Jun 25 2014, 12:09:21

    Freescale Semiconductor, Inc.

******************************

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is LPDDR2 in 1-channel mode.

Data width: 32, bank num: 8

Row size: 14, col size: 9

Chip select CSD0 is used

Density per chip select: 256MB

==================================

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz

  ARM set to 800MHz

Please select the DDR density per CHANNEL (in bytes) on the board

Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6

for 32MB

Note, if there are two chip selects per channel, then input the combined densit

y of

  both chip selects per channel

  DDR density selected (MB): 2048

  CHANNEL0 is selected.

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.

If you want to run at other DDR frequency. Type 'n'

  DDR Freq: 528 MHz

Would you like to run the read/write calibration? (y/n)

Note: Array result[] holds the DRAM test result of each byte.

      0: test pass.  1: test fail

      4 bits respresent the result of 1 byte.

      result 0001:byte 0 fail.

      result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000   result[00]=0x1111

ABS_OFFSET=0x04040404   result[01]=0x1111

ABS_OFFSET=0x08080808   result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C   result[03]=0x1111

ABS_OFFSET=0x10101010   result[04]=0x1111

ABS_OFFSET=0x14141414   result[05]=0x1111

ABS_OFFSET=0x18181818   result[06]=0x1111

ABS_OFFSET=0x1C1C1C1C   result[07]=0x1111

ABS_OFFSET=0x20202020   result[08]=0x1111

ABS_OFFSET=0x24242424   result[09]=0x1111

ABS_OFFSET=0x28282828   result[0A]=0x1111

ABS_OFFSET=0x2C2C2C2C   result[0B]=0x1111

ABS_OFFSET=0x30303030   result[0C]=0x1111

ABS_OFFSET=0x34343434   result[0D]=0x1111

ABS_OFFSET=0x38383838   result[0E]=0x1111

ABS_OFFSET=0x3C3C3C3C   result[0F]=0x1111

ABS_OFFSET=0x40404040   result[10]=0x1111

ABS_OFFSET=0x44444444   result[11]=0x1111

ABS_OFFSET=0x48484848   result[12]=0x1111

ABS_OFFSET=0x4C4C4C4C   result[13]=0x1111

ABS_OFFSET=0x50505050   result[14]=0x1111

ABS_OFFSET=0x54545454   result[15]=0x1111

ABS_OFFSET=0x58585858   result[16]=0x1111

ABS_OFFSET=0x5C5C5C5C   result[17]=0x1111

ABS_OFFSET=0x60606060   result[18]=0x1111

ABS_OFFSET=0x64646464   result[19]=0x1111

ABS_OFFSET=0x68686868   result[1A]=0x1111

ABS_OFFSET=0x6C6C6C6C   result[1B]=0x1111

ABS_OFFSET=0x70707070   result[1C]=0x1111

ABS_OFFSET=0x74747474   result[1D]=0x1111

ABS_OFFSET=0x78787878   result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C   result[1F]=0x1111

ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Srinivasa

one can try suggestions for configuring lpddr2 with i.MX6DQ

MX6Q+LPDDR2(32bit) boot issue

Best regards

igor

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igorpadykov
NXP TechSupport
NXP TechSupport

one can add to init script file pad control settings, like

sect.36.4.319 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P),

36.4.353 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P)

i.MX6DQ Reference Manual (rev.2  7/2014)

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

~igor

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Srinivasa

density per chip select: 256MB (bytes) is the same as 2Gb (bits).

Had test finished with lower arm requencies, like 800MHz,

If yes then you can use its results. Problems with running 1.2GHz

could be that not all parts can run at such frequency , it should has

"12" suffix, like "MCIMX6D5EYM12AC" and  run at VDDARM_IN =1.4V–1.5V

only in LDO mode (LDO output at 1.275V).

Otherwise processor can hang executing any other code, not only DDR test.

Best regards

igor

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srinivasaporam
Contributor II

Hi,

Thanks for the reply. Can you please tell me how i can select SI Configuration values.

 

DRAM DSE Setting - DQ/DQM (ohm)
DRAM DSE Setting - ADDR/CMD/CTL (ohm)
DRAM DSE Setting - CK (ohm)
DRAM DSE Setting - DQS (ohm)

trial and error will be tedious.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Srinivasa

selection of DSE settings is performed by trial method.

Other way - use ibis modelling.

Best regards

igor

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