DDR Stress Test failed for IMX8QM Custom Board

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DDR Stress Test failed for IMX8QM Custom Board

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vinothkumars
Senior Contributor III

Dear NXP,

 

DDR stress test failed. Will you please give some idea regarding the following errors,

 

*************************************************************************
MX8 DDR Stress Test Version: ER14
Built on Mar 27 2020 12:19:30
*************************************************************************

--Set up the MMU and enable I and D cache--
- This is the Cortex-A72 core
Adjusting CA72 cache latency
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x13d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1124

- MMU and cache setup complete

*************************************************************************
ARM Clock(CA72): 1596MHz
DDR Clock: 1596MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 15, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 2
Density per chip select: 1024MB
Density per controller is: 2048MB
Total density detected on the board is: 4096MB

Note: As this SoC has more than one DDR Controller, the calculated
density assumes all controllers are being used. Adjust the tested
density per your board configuration if not all controllers are used

 

********************************************
WARNING! DDR training errors were detected on DDRC 0!
DDR_PHY_PGSR0 = 0x806cc07f
DQS Gate training error detected
Write Leveling training error detected
VREF training error detected
Write DQS2DQ training error detected
Recheck DDR initialization
********************************************


********************************************
WARNING! DDR training errors were detected on DDRC 1!
DDR_PHY_PGSR0 = 0x806cc07f
DQS Gate training error detected
Write Leveling training error detected
VREF training error detected
Write DQS2DQ training error detected
Recheck DDR initialization
********************************************
============================================

MX8QM: Cortex-A72 is found

*************************************************************************

 

 

Regards,
Vinothkumar Sekar
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1 Solution
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igorpadykov
NXP TechSupport
NXP TechSupport

I believe Chan B is configured incorrectly. For example:
on your schematic DQ0_B (pad AA2) is connected to DDR0_B_DQ4 (DDR_CH0_DQ20)
so Excel "BoardDataBusConfig" Chan B should be:
DRAM Data bus 0
MX8QM data bus (User Input)-> 20

DQ1_B (pad Y2) is connected to DDR0_B_DQ7 (DDR_CH0_DQ23)

so Excel "BoardDataBusConfig" should be:
DRAM Data bus 1
MX8QM data bus (User Input)-> 23

e.t.c.

 

Best regards
igor

 

 

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3 Replies
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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Vinothkumar

 

reason for this issue may be wrong memory connections or incorrectly configured "BoardDataBusConfig"

parameters in RPA tool.

 

Best regards
igor

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vinothkumars
Senior Contributor III

Thank you @igorpadykov  for the reply.

 

Will you please validate my BoardDataBusConfig section for DDRC0.

 

 

DDRC0.png

DDRC0_1.png

  

 

Regards,
Vinothkumar Sekar
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39 Views
igorpadykov
NXP TechSupport
NXP TechSupport

I believe Chan B is configured incorrectly. For example:
on your schematic DQ0_B (pad AA2) is connected to DDR0_B_DQ4 (DDR_CH0_DQ20)
so Excel "BoardDataBusConfig" Chan B should be:
DRAM Data bus 0
MX8QM data bus (User Input)-> 20

DQ1_B (pad Y2) is connected to DDR0_B_DQ7 (DDR_CH0_DQ23)

so Excel "BoardDataBusConfig" should be:
DRAM Data bus 1
MX8QM data bus (User Input)-> 23

e.t.c.

 

Best regards
igor

 

 

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