hi nxp
my board cpu is imd8dx 16bit LPDDR4,please the fail, Can you provide me with some help to fix the error。
*************************************************************************
MX8 DDR Stress Test Version: ER14
Built on Mar 27 2020 12:28:23
*************************************************************************
--Set up the MMU and enable I and D cache--
- This is the Cortex-A35 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x13d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x101122
- MMU and cache setup complete
*************************************************************************
ARM Clock(CA35): 1200MHz
DDR Clock: 1200MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 16, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1024MB
Density per controller is: 1024MB
Total density detected on the board is: 1024MB
********************************************
WARNING! DDR training errors were detected on DDRC 0!
DDR_PHY_PGSR0 = 0x806cc07f
DQS Gate training error detected
Write Leveling training error detected
VREF training error detected
Write DQS2DQ training error detected
Recheck DDR initialization
********************************************
============================================
MX8QXP: Cortex-A35 is found
Hi Hongliang
since all trainings are with errors, one can check with oscilloscope if there are any signals
on memory. Also recommended to use latest MX8DualX_C0_B0_LPDDR4_RPA_1.2GHz_v16.xlsx on
Best regards
igor
HI,
I have used the latest scfw1.7.0 and MX8DualX_C0_B0_LPDDR4_RPA_1.2GHz_v16.xls。
>I have used the latest scfw1.7.0..
it is not latest, latest is v1.10.0 SCFW Porting Kit 1.10.0
Best regards
igor