DDR Hardware Calibration in flash_header.S

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DDR Hardware Calibration in flash_header.S

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alexhe
Contributor I

Hi,


I was wondering if there are any samples of running the hardware ZQ calibration, write leveling, DQS gating\read\write within flash_header.S.

I've modified the DCD table with new calibration values after running the MX6 DDR Stress Test Tool. However, these values only work on one board and moving onto another board, I run into memory issues again. Therefore, I want to implement running calibration on every boot for each individual board. My understanding is that it should be done flash_header.S, but I'm not entirely sure how to go about doing it. Any help would be great.

Thanks,

Alex

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Alex

unfortunately calibration routine can not be run within flash_header.S.

It is too complex for that and described in application Note AN4467 (Rev. 0, 10/2012)

"i.MX 6 Series DDR Calibration"

http://www.freescale.com/files/32bit/doc/app_note/AN4467.pdf

Best regards

chip

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alexhe
Contributor I

Thanks Chip.

ZQ calibration appears to be done within flash_header.S so I was thinking the other calibration might be done within as well.


I am trying to use manufacturing utility to bringup boards, but quite a few boards are failing with what appears to be memory issues. On a few boards, after running the DDR calibration tool from the MX6 DDR Stress Test Tool and modifying the DCD table with these new values and rebuilding manufacturing u-boot, they appear to behave better. Since the manufacturing utility is before any code can be executed, I can't think of a way to do any of the other calibration besides in flash_header.S. Do you have any suggestions on how to tackle this issue?

Thanks,

Alex

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Alex

again, calibration routine can not be run within flash_header.S.

flash_header.S uses values got in DDR tests

https://community.freescale.com/message/331721#331721

https://community.freescale.com/docs/DOC-96412

Manufacturing utility firmware (initramfs.cpio.gz.uboot)

should be rebuilt also for usage with new board.

Best regards

chip

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bradlepper
Contributor I

Hello Chip,

You said twice in this thread that the calibration routine cannot be run within flash_header.S.  Is there any way to automate that calibration at all within the bootloader so that the calibration could be performed automatically on the first boot or our boards?  We are finding that our LPDDR2 is very sensitive to the read and write MPRDDLCTL PHY0/PHY1 and MPWRDLCTL PHY0/PHY1 register values.  We were hoping that we could run the Windows DDR stress tester (v1.03) program on a sample set of our production boards to get an average value for these registers that would work for all boards and hard code them into our flash_header.S file.  However, whenever we try to use an average values for these boards, we are seeing that some boards work fine under a memory stress tester, but other boards get bit-flips and other RAM integrity errors.  We are coming to the conclusion that we may have to run calibration on every board.  Is it a common practice to run this calibration on every board?  Or do most people find average values that they can hard code into the flash_header.S that work reliably on every board?

If we end up needing to run calibration on every board, doing DDR calibration on every board in production puts a huge time burden on our production flow, so we are considering ways to automate the DDR calibration in the software that runs on the board, so that it will calibrate itself on the first boot.  Has anyone done any work to automate this calibration in u-boot?  Any recommendations or information on getting this calibration automated would be very helpful.

Thank You,

Brad

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fabio_estevam
NXP Employee
NXP Employee

Hi Brad,

I suggest you to take a look at the mx6 spl support that has been recently added into U-boot mainline, that allows DDR calibration dynamically.

See this commit for example:

http://git.denx.de/?p=u-boot.git;a=commitdiff;h=8d05b161fc4633788bcad133efdf8d76fc40237f

I am not familiar with the U-boot spl support yet, but I would recommend you to take a look at the existing spl support for mx6 and ask in the U-boot list if you have questions on this topic.

Hope this helps.

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