Hello,
When I check the reference schematic on AN5161,
DDR Data lines between i.MX 6SoloX and DDR Memory are not connected as below
Data0 to Data0, Data1 to Data1, .... Data31 to Data31.
Instead, the connection is complicated like
Data0 - Data16, Data1 - Data17,...
What is the reason of the DDR Data connection like that?
Can we connect them according to Data Number order as normal?
Thanks,
Andy