Hi ALL,
I have changed some of the drive strength parameters in DDR config code, all DDR calibration tests are passing.
But I configured Write levelling parameters as:
0x021b080c = 0x001F001F
0x021b0810 = 0x001F001F
0x021b480c = 0x001F001F
0x021b4810 = 0x001F001F
and output values are:
Start write leveling calibration
Write leveling calibration completed
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x004E0051
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00420048
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00330031
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x0030003F
could please help me, the output values are larger than configured values?
Do i need to change any configuration parameters.
Please suggest me.
Dear NxP support Team,
Issue: After executing DDR calibration code, not able to load application from flash memory.
We have integrated DDR calibration source code(provided by nxp, version 1.0.2) to our customized boot loader. After clock, pinmux, and ddr initilization, we executed the DDR calibration tests(writeleveling, DQS gating, read & write calibration). After executing DDR calibration tests, not running the system.
it some times hangs in uart initilization...etc.
results:
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x00500058
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x0042004B
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00330035
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x0036004B
Starting DQS gating calibration...
. HC_DEL=0x 0 result[ 0]=0x 1001011
. HC_DEL=0x 1 result[ 1]=0x 1001
. HC_DEL=0x 2 result[ 2]=0x 0
. HC_DEL=0x 3 result[ 3]=0x11000000
. HC_DEL=0x 4 result[ 4]=0x11111111
. HC_DEL=0x 5 result[ 5]=0x11111111
. HC_DEL=0x 6 result[ 6]=0x11111111
. HC_DEL=0x 7 result[ 7]=0x11111111
. HC_DEL=0x 8 result[ 8]=0x11111111
. HC_DEL=0x 9 result[ 9]=0x11111111
. HC_DEL=0x A result[ A]=0x11111111
. HC_DEL=0x B result[ B]=0x11111111
. HC_DEL=0x C result[ C]=0x11111111
. HC_DEL=0x D result[ D]=0x11111111
DQS HC delay value low1 = 0x 406, high1=0x 605070C
DQS HC delay value low2 = 0x 5090202, high2=0x B0B0505
loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x 0 result[ 0]=0x11001001
. ABS_OFFSET=0x 4 result[ 1]=0x11001001
. ABS_OFFSET=0x 8 result[ 2]=0x11001001
. ABS_OFFSET=0x C result[ 3]=0x11001001
. ABS_OFFSET=0x 10 result[ 4]=0x11001001
. ABS_OFFSET=0x 14 result[ 5]=0x11001001
. ABS_OFFSET=0x 18 result[ 6]=0x11001001
. ABS_OFFSET=0x 1C result[ 7]=0x11001001
. ABS_OFFSET=0x 20 result[ 8]=0x11001001
. ABS_OFFSET=0x 24 result[ 9]=0x11001011
. ABS_OFFSET=0x 28 result[ A]=0x11001011
. ABS_OFFSET=0x 2C result[ B]=0x11001011
. ABS_OFFSET=0x 30 result[ C]=0x11001011
. ABS_OFFSET=0x 34 result[ D]=0x11001011
. ABS_OFFSET=0x 38 result[ E]=0x11001011
. ABS_OFFSET=0x 3C result[ F]=0x11001011
. ABS_OFFSET=0x 40 result[10]=0x11001011
. ABS_OFFSET=0x 44 result[11]=0x11001011
. ABS_OFFSET=0x 48 result[12]=0x11001011
. ABS_OFFSET=0x 4C result[13]=0x11001011
. ABS_OFFSET=0x 50 result[14]=0x11001011
. ABS_OFFSET=0x 54 result[15]=0x11001011
. ABS_OFFSET=0x 58 result[16]=0x11001011
. ABS_OFFSET=0x 5C result[17]=0x11001011
. ABS_OFFSET=0x 60 result[18]=0x11001011
. ABS_OFFSET=0x 64 result[19]=0x11001011
. ABS_OFFSET=0x 68 result[1A]=0x11001011
. ABS_OFFSET=0x 6C result[1B]=0x11001011
. ABS_OFFSET=0x 70 result[1C]=0x11001011
. ABS_OFFSET=0x 74 result[1D]=0x11001011
. ABS_OFFSET=0x 78 result[1E]=0x11001011
. ABS_OFFSET=0x 7C result[1F]=0x11001011
loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x 0 result[ 0]=0x11111111
. ABS_OFFSET=0x 4 result[ 1]=0x11111111
. ABS_OFFSET=0x 8 result[ 2]=0x11111111
. ABS_OFFSET=0x C result[ 3]=0x11111111
. ABS_OFFSET=0x 10 result[ 4]=0x11111111
. ABS_OFFSET=0x 14 result[ 5]=0x11111111
. ABS_OFFSET=0x 18 result[ 6]=0x11111111
. ABS_OFFSET=0x 1C result[ 7]=0x11111111
. ABS_OFFSET=0x 20 result[ 8]=0x11111111
. ABS_OFFSET=0x 24 result[ 9]=0x11111111
. ABS_OFFSET=0x 28 result[ A]=0x11111111
. ABS_OFFSET=0x 2C result[ B]=0x11111111
. ABS_OFFSET=0x 30 result[ C]=0x11111111
. ABS_OFFSET=0x 34 result[ D]=0x11111111
. ABS_OFFSET=0x 38 result[ E]=0x11111111
. ABS_OFFSET=0x 3C result[ F]=0x11111111
. ABS_OFFSET=0x 40 result[10]=0x11111111
. ABS_OFFSET=0x 44 result[11]=0x11111111
. ABS_OFFSET=0x 48 result[12]=0x11111111
. ABS_OFFSET=0x 4C result[13]=0x11111111
. ABS_OFFSET=0x 50 result[14]=0x11111111
. ABS_OFFSET=0x 54 result[15]=0x11111111
. ABS_OFFSET=0x 58 result[16]=0x11111111
. ABS_OFFSET=0x 5C result[17]=0x11111111
. ABS_OFFSET=0x 60 result[18]=0x11111111
. ABS_OFFSET=0x 64 result[19]=0x11111111
. ABS_OFFSET=0x 68 result[1A]=0x11111111
. ABS_OFFSET=0x 6C result[1B]=0x11111111
. ABS_OFFSET=0x 70 result[1C]=0x11111111
. ABS_OFFSET=0x 74 result[1D]=0x11111111
. ABS_OFFSET=0x 78 result[1E]=0x11111111
. ABS_OFFSET=0x 7C result[1F]=0x11111111
BYTE 0:
Start: HC=0x 5 ABS=0x 0
End: HC=0x C ABS=0x20
Mean: HC=0x 8 ABS=0x4F
End-0.5*tCK: HC=0x B ABS=0x20
Final: HC=0x B ABS=0x20
BYTE 1:
Start: HC=0x 3 ABS=0x 0
End: HC=0x 7 ABS=0x20
Mean: HC=0x 5 ABS=0x10
End-0.5*tCK: HC=0x 6 ABS=0x20
Final: HC=0x 6 ABS=0x20
BYTE 2:
Start: HC=0x 0 ABS=0x 0
End: HC=0x 5 ABS=0x78
Mean: HC=0x 2 ABS=0x7B
End-0.5*tCK: HC=0x 4 ABS=0x78
Final: HC=0x 4 ABS=0x78
BYTE 3:
Start: HC=0x 0 ABS=0x 0
End: HC=0x 6 ABS=0x78
Mean: HC=0x 3 ABS=0x3C
End-0.5*tCK: HC=0x 5 ABS=0x78
Final: HC=0x 5 ABS=0x78
BYTE 4:
Start: HC=0x 1 ABS=0x 0
End: HC=0x 5 ABS=0x C
Mean: HC=0x 3 ABS=0x 6
End-0.5*tCK: HC=0x 4 ABS=0x C
Final: HC=0x 4 ABS=0x C
BYTE 5:
Start: HC=0x 1 ABS=0x 8
End: HC=0x 5 ABS=0x C
Mean: HC=0x 3 ABS=0x A
End-0.5*tCK: HC=0x 4 ABS=0x C
Final: HC=0x 4 ABS=0x C
BYTE 6:
Start: HC=0x 8 ABS=0x 0
End: HC=0x B ABS=0x70
Mean: HC=0x 9 ABS=0x77
End-0.5*tCK: HC=0x A ABS=0x70
Final: HC=0x A ABS=0x70
BYTE 7:
Start: HC=0x 4 ABS=0x 0
End: HC=0x B ABS=0x78
Mean: HC=0x 7 ABS=0x7B
End-0.5*tCK: HC=0x A ABS=0x78
Final: HC=0x A ABS=0x78
DQS calibration MMDC0 MPDGCTRL0 = 0x46200B20, MPDGCTRL1 = 0x 5780478
DQS calibration MMDC1 MPDGCTRL0 = 0x440C040C, MPDGCTRL1 = 0x A780A70
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x 0 result[ 0]=0x11111111
ABS_OFFSET=0x 4040404 result[ 1]=0x11111111
ABS_OFFSET=0x 8080808 result[ 2]=0x11111111
ABS_OFFSET=0x C0C0C0C result[ 3]=0x11111111
ABS_OFFSET=0x10101010 result[ 4]=0x11111111
ABS_OFFSET=0x14141414 result[ 5]=0x11111111
ABS_OFFSET=0x18181818 result[ 6]=0x11111111
ABS_OFFSET=0x1C1C1C1C result[ 7]=0x11111111
ABS_OFFSET=0x20202020 result[ 8]=0x11111111
ABS_OFFSET=0x24242424 result[ 9]=0x11111111
ABS_OFFSET=0x28282828 result[ A]=0x11111111
ABS_OFFSET=0x2C2C2C2C result[ B]=0x11111111
ABS_OFFSET=0x30303030 result[ C]=0x11111111
ABS_OFFSET=0x34343434 result[ D]=0x 1111111
ABS_OFFSET=0x38383838 result[ E]=0x 1111111
ABS_OFFSET=0x3C3C3C3C result[ F]=0x 1111111
ABS_OFFSET=0x40404040 result[10]=0x11111111
ABS_OFFSET=0x44444444 result[11]=0x11111111
ABS_OFFSET=0x48484848 result[12]=0x11111111
ABS_OFFSET=0x4C4C4C4C result[13]=0x11111111
ABS_OFFSET=0x50505050 result[14]=0x11111111
ABS_OFFSET=0x54545454 result[15]=0x11111111
ABS_OFFSET=0x58585858 result[16]=0x11111111
ABS_OFFSET=0x5C5C5C5C result[17]=0x11111111
ABS_OFFSET=0x60606060 result[18]=0x11111111
ABS_OFFSET=0x64646464 result[19]=0x11111111
ABS_OFFSET=0x68686868 result[1A]=0x11111111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPRDDLCTL = 0x70006E6E, MMDC1 MPRDDLCTL = 0x30347272
Starting Write calibration...
ABS_OFFSET=0x 0 result[ 0]=0x11111111
ABS_OFFSET=0x 4040404 result[ 1]=0x11111111
ABS_OFFSET=0x 8080808 result[ 2]=0x11111111
ABS_OFFSET=0x C0C0C0C result[ 3]=0x11111111
ABS_OFFSET=0x10101010 result[ 4]=0x11111111
ABS_OFFSET=0x14141414 result[ 5]=0x11111111
ABS_OFFSET=0x18181818 result[ 6]=0x11111111
ABS_OFFSET=0x1C1C1C1C result[ 7]=0x 1111111
ABS_OFFSET=0x20202020 result[ 8]=0x 1111111
ABS_OFFSET=0x24242424 result[ 9]=0x11111111
ABS_OFFSET=0x28282828 result[ A]=0x11111111
ABS_OFFSET=0x2C2C2C2C result[ B]=0x11111111
ABS_OFFSET=0x30303030 result[ C]=0x11111111
ABS_OFFSET=0x34343434 result[ D]=0x11111111
ABS_OFFSET=0x38383838 result[ E]=0x11111111
ABS_OFFSET=0x3C3C3C3C result[ F]=0x11111111
ABS_OFFSET=0x40404040 result[10]=0x11111111
ABS_OFFSET=0x44444444 result[11]=0x11111111
ABS_OFFSET=0x48484848 result[12]=0x11111111
ABS_OFFSET=0x4C4C4C4C result[13]=0x11111111
ABS_OFFSET=0x50505050 result[14]=0x11111111
ABS_OFFSET=0x54545454 result[15]=0x11111111
ABS_OFFSET=0x58585858 result[16]=0x11111111
ABS_OFFSET=0x5C5C5C5C result[17]=0x11111111
ABS_OFFSET=0x60606060 result[18]=0x11111111
ABS_OFFSET=0x64646464 result[19]=0x11111111
ABS_OFFSET=0x68686868 result[1A]=0x11111111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPWRDLCTL = 0x70683838,MMDC1 MPWRDLCTL = 0x24206E6E
MMDC registers updated from calibration
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x46200B20
MPDGCTRL1 PHY0 (0x021b0840) = 0x05780478
MPDGCTRL0 PHY1 (0x021b483c) = 0x440C040C
MPDGCTRL1 PHY1 (0x021b4840) = 0x0A780A70
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x70006E6E
MPRDDLCTL PHY1 (0x021b4848) = 0x30347272
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x70683838
MPWRDLCTL PHY1 (0x021b4850) = 0x24206E6E
Hello,
Please try the recent DDR Stress test :
https://community.nxp.com/docs/DOC-105652
Regards,
Yuri.
Hello,
I do not think that it is required to change calibration values, if memory
tests are passed after initialization with found calibration values.
Nevertheless, please take a look at section 3.1.1 (Write Leveling Calibration)
of Freescale i.MX6 DRAM Port Application Guide-DDR3
Have a great day,
Yuri
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