DDR Access from M4 when A7 is in VLLS (IMX7ULP)

[vivekrajpara]

Hello,

In our setup, we want to put A7 in very low power mode but at the same time, we want to access DDR from the Cortex M4. 

The main reason for this design to have around 10MB available with M4.

Can anyone please let us know if this is possible or not, it is a deciding factor for our solution, looking forward to quick confirmation on this fact, also if possible, it would be great if someone can share some sample or document explaining process for performing such operations.

Thanks,

Vivek

[igorpadykov · Accepted solution]

Hi Vivek

for A7 in VLLS mode cases one can look at sect.5.3.2 Real-time domain (M4) active power measurements

i.MX 7ULP Power Consumption Measurement

However, seems access DDR from the Cortex M4 is not allowed in such cases as

MMDC belongs to Application domain (Cortex-A7).

Best regards
igor
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[vivekrajpara]

Thanks a lot, Igor for this confirmation.