Hello *,
Scenario:
IMX6 SSI connected to CODEC and another FPGA SSI on the same wires.
The two SSI write audio in the same TX data in TDM (Time Division Multiplexing) using different channel obviously.
The FPGA SSI write on first channel (left) and provide BCLK and LRCLK, leaving 3 channels stereo 16bit for each frame.
The IMX should write on second channel LEFT and RIGHT.
But, if I play a PCM 16 bit stereo, it write on second channel left only, so the sound slowly because the right channel is used on next left channel.
Now, there is a particular option that permit to write in the RIGHT channel?
I tried to use 3 channels but it appear only in the third Left channel (so the pcm left is on second channel, the pcm right is on third, but nothing on right channels.
Regards
Solved! Go to Solution.
Hi Cristian
right, not possible. Network mode has not option
of "STEREO option", "Right" or "Left" channels. There are
just timing slots, of course you can put there anything:
right or left data, as necessary. But you should program SSI
appropriately and write own driver for that.
Also Frame Sync can not be such length as in your diagram.
Sect. 61.8.1.2 Network Mode IMX6DQRM
TFSL register SSIx_STCR gives Frame Sync only option as :
Transmit Frame Sync Length. This bit controls the length of the frame sync signal to be generated or
recognized for the transmit section. The length of a word-long frame sync is same as the length of the data
word selected by WL[3:0].
0 ONE_WORD — Transmit frame sync is one-word long.
1 ONE_CLOCK_BIT — Transmit frame sync is one-clock-bit long.
~igor
Hi Cristian
one can use Network mode, frame sync ("LRCLK" in your notation)
should be SSIx_STCR register, bit TFSL Transmit Frame Sync Length.
Diagrams are given in Figure 61-15. Network Mode Timing - Continuous Clock,
sect.61.8.1.2 Network Mode IMX6DQRM
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Really thank's for reply.
I tried with TFSL set, but it don't work, the sincronizzation is bad (consider that the IMX is SLAVE respect to FPGA).
Setting the TFSL, in network mode, it expect a DSP MODE B, from the SSI driver:
case SND_SOC_DAIFMT_LEFT_J:
/* data on rising edge of bclk, frame high with data */
strcr |= SSI_STCR_TXBIT0;
break;
case SND_SOC_DAIFMT_DSP_B:
/* data on rising edge of bclk, frame high with data */
strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0;
break;
The strange things is that the correct mode should be LEFT JUSTIFIED:
Seems that there is a "STEREO option" disabled.
in Network mode there is no "STEREO option".
Thank you igorpadykov,
so is not possible have a configuration like this?
if is not possible, there are a way to suppress the right channel automatically (due to avoid that RIGHT channel data will write on the next LEFT channel)?
Hi Cristian
right, not possible. Network mode has not option
of "STEREO option", "Right" or "Left" channels. There are
just timing slots, of course you can put there anything:
right or left data, as necessary. But you should program SSI
appropriately and write own driver for that.
Also Frame Sync can not be such length as in your diagram.
Sect. 61.8.1.2 Network Mode IMX6DQRM
TFSL register SSIx_STCR gives Frame Sync only option as :
Transmit Frame Sync Length. This bit controls the length of the frame sync signal to be generated or
recognized for the transmit section. The length of a word-long frame sync is same as the length of the data
word selected by WL[3:0].
0 ONE_WORD — Transmit frame sync is one-word long.
1 ONE_CLOCK_BIT — Transmit frame sync is one-clock-bit long.
~igor