Could someone tell me a configuration of L2 Cache latency?

[T-Ii]

I want to know which latency is chosen in L2CTLR_EL1 register of i.MX8M Nano UL Solo.

Could you open it?

https://developer.arm.com/documentation/ddi0500/j/System-Control/AArch64-register-descriptions/L2-Co...

Thanks