Confused about the SRAM size description in RT595 datasheet

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Confused about the SRAM size description in RT595 datasheet

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Dave_SU
Contributor III

Hi,

As we know, RT595 has up to 5 MB SRAM. But in the system memory map section of the datasheet, we can see that there are two RAM banks.

One is shared RAM partitions 0-31 via M33 code bus(overlaps data region) , which address area is 0x00000000- 0x00500000.

The other is shared RAM partitions 0-1 via data bus(overlaps M33 code region), which address area is  0x20000000-0x20500000.

Why are there two RAM areas and what are their functions? How is the 5M RAM of RT500 allocated.

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nxf77486
NXP Employee
NXP Employee

Hello @Dave_SU ,

In the datasheet Chapter 2 Memory Maps, you will find the following information:
-------------------------------------------------------------------------------------------------------------------

All SRAM partitions are accessible by both CPUs or by any other AHB bus master (including the DMAs). The Fusion DSP

accesses these ram partitions via its dedicated, tightly-couple memory (TCM) buses. The GPU and the LCD Display Interface

(Display Controller) will access this ram via dedicated 64:bit AHB buses.

All of the SRAMs will be mapped into both the Code and Data address spaces of the M33

processor so any of the partitions may be accessed from either the C-code or System buses. Partitions will be distributed among

several AHB slave ports (on each matrix) to minimize conflicts.

-------------------------------------------------------------------------------------------------------------------

So in the table 3. Shared RAM Address Map you will find the corresponding address for this shared RAM.

That is divided for 3 different addresses.

  1. M33 code/DSP code address.
  2. Fusion DSP Data address
  3. All the other AHB masters (including M33 System bus & DMA).

Please let me know if this answer is helpful or if you have any other question I will be happy to assist you.

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Dave_SU
Contributor III

@nxf77486 

thank you for your reply

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202 Views
nxf77486
NXP Employee
NXP Employee

Hello @Dave_SU ,

In the datasheet Chapter 2 Memory Maps, you will find the following information:
-------------------------------------------------------------------------------------------------------------------

All SRAM partitions are accessible by both CPUs or by any other AHB bus master (including the DMAs). The Fusion DSP

accesses these ram partitions via its dedicated, tightly-couple memory (TCM) buses. The GPU and the LCD Display Interface

(Display Controller) will access this ram via dedicated 64:bit AHB buses.

All of the SRAMs will be mapped into both the Code and Data address spaces of the M33

processor so any of the partitions may be accessed from either the C-code or System buses. Partitions will be distributed among

several AHB slave ports (on each matrix) to minimize conflicts.

-------------------------------------------------------------------------------------------------------------------

So in the table 3. Shared RAM Address Map you will find the corresponding address for this shared RAM.

That is divided for 3 different addresses.

  1. M33 code/DSP code address.
  2. Fusion DSP Data address
  3. All the other AHB masters (including M33 System bus & DMA).

Please let me know if this answer is helpful or if you have any other question I will be happy to assist you.

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