Conflicting documentation on boot config pins for IMX6UL

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Conflicting documentation on boot config pins for IMX6UL

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gerardobarroeta
Contributor I

On Document SPF-28617_C5 (Schematics of DevBoard), Sheet 9, first table at top left, under column: BOOT_CFG1[3], row MMC/eMMC, the cell states that a 0 configures eMMC for High speed, and a 1 sets it to low speed.

However, in the reference manual (http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf), page 274, Table8-15, top row (0x450[3:2]) it states the opposite: MMC 0x - Normal Speed Mode, 1x - High Speed mode.

Which one is it??

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Yuri
NXP Employee
NXP Employee

Hello,

  The RM is correct : MMC 0x - Normal Speed Mode, 1x - High Speed mode.

Thanks for Your pointing this inaccuracy in the schematic table.  

Regards,

Yuri.

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