Conflict with clock between LCD and HDMI on i.MX6Q.

[EgleTeam]

Hello,

We are trying to make work 3 displays at the same time with an iMX6Q: LCD+LVDS+HDMI.

The config is the following:

//--------------------------------------------------

static struct ipuv3_fb_platform_data es6_fb_data[] = {

{

      .disp_dev = "lcd",

      .interface_pix_fmt = IPU_PIX_FMT_RGB666,

      .mode_str = "SEIKO-WVGA",

      .default_bpp = 18,

      .int_clk = false,

      .late_init = false,

},

{

      .disp_dev = "ldb",

      .interface_pix_fmt = IPU_PIX_FMT_RGB666,

      .mode_str = "LDB-WXGA",

      .default_bpp = 18,

      .int_clk = false,

      .late_init = false,

},

{

      .disp_dev = "hdmi",

      .interface_pix_fmt = IPU_PIX_FMT_RGB24,

      .mode_str = "1920x1080M@60",

      .default_bpp = 32,

      .int_clk = false,

      .late_init = false,

},

};

//--------------------------------------------------

static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {

.ipu_id = 0,

.disp_id = 1,

};

static struct fsl_mxc_lcd_platform_data lcdif_data = {

.ipu_id = 0,

.disp_id = 0,

.default_ifmt = IPU_PIX_FMT_RGB666,

};

static struct fsl_mxc_ldb_platform_data ldb_data = {

.ipu_id = 1,

.disp_id = 0,

.ext_ref = 1,

.mode = LDB_SIN0,

};

//--------------------------------------------------

LCD+LVDS and HDMI+LVDS work right. The problem is when we "unblank" LCD and HDMI at the same time: It doesn't work and we get the following errors:

imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_10 = 0x00080000

imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_5 = 0x00800000

imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_10 = 0x00100000

imx-ipuv3 imx-ipuv3.0: IPU Warning - IPU_INT_STAT_5 = 0x10000000

It happens like if both interfaces would share the same clock. I mean: if the LCD is working and we turn on the HDMI then the LCD "goes crazy" and we can see 150Mhz on its clock line using a probe, and If the HDMI is working and we turn on the LCD then the HDMI stops working and we can see 33Mhz on its clock (same frequency than LCD clock).

LCD is on DISP0. We've tried all the combinations between IPUs and DIs but always happens the same.

Any advice?. Thanks,

Manuel.

[EgleTeam]

We managed to put on the 3 displays at the same time but only with few resolutions on the HDMI port (800x480@60, 640x480@60, 720x576@60 and 1280x1024@60): 1920x1080@60 (and many more) still giving us problems. I will ask 2 particular questions to see if someone could help us:

1. Is the clock frequency of each display port of an IPU fully configurable and independent from the other one?.

2. What GPRs or linux functions (better this option) could we use to check and modify the clock of the display ports?

Regards.

[PeterChan]

1. Is the clock frequency of each display port of an IPU fully configurable and independent from the other one?

Each IPU display port source can be sourced from one of the following clock sources: mmdc_ch0_axi_clk, pll3_usb_otg_main_clk, pll5_video_main_clk, pll2_pfd0_352M,  pll2_pfd2_400M & pll3_pfd1_540M, via the register CHSCCDR/CSCDR2::ipuX_diX_pre_clk_sel. Each IPU display port can also be sourced from either ldb_di0_ipu or ldb_di1_ipu by CHSCCDR/CSCDR2::ipuX_diX_clk_sel for LDB connection. For detail, please refer to page 834-835 in i.MX6DQ reference manual.

LCD & HDMI clocks will have dependence to each other if they are driven by the same clock source (pll5_video_main_clk in BSP) and sharing the same ipu_id.

2. What GPRs or linux functions (better this option) could we use to check and modify the clock of the display ports?

The shell script "/unit_tests/dump-clocks.sh" in rootfs can be used to display the MX6 clock tree. The "unit_tests/memtool" can help to dump register values. You can make use of these tools to check the display clock.

[EgleTeam]

Thanks Peter,

I will pay attention to those registers.

Best regards,

Manuel.