Confirm about i.MX6 ASRC.

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Confirm about i.MX6 ASRC.

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satoshishimoda
Senior Contributor I

Hi community,

I want to confirm about i.MX6 ASRC.

Please my questions below.

[Q1]

Please see Figure 15-4 in IMX6SDLRM (Rev.1).

There are input clock A, B, C and output clock A, B, C.

I understand these input clocks are the sampling rate for audio data from external device.

And these output clocks are the sampling rate for audio data to external device.

Is my understanding correct?

[Q2]

Please see Table 15-7.

I want to confirm correspondence between "Fsin, Fsout" in this table and "input clock, output clock" in Figure 15-4.

Could you let me know it?

[Q3]

Please see ATSC bit in chapter 15.7.1.

Could you let me know how ASRC decide a sampling rate for input / output if ATSC is set?

Best Regards,

Satoshi Shimoda

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Bio_TICFSL
NXP TechSupport
NXP TechSupport

1) Is my understanding correct?

A1. The main function of ARSC is Converting the sampling rate of a signal associated  to an input clock into a signal associated to a different output clock. Clocks shall be physically available e.g. Different clock sources, with different dividers

SSI/ESAI      --- normally divide 64

SPDIF(Rx)    --- normally divide 128

[Q2]Please see Table 15-7.I want to confirm correspondence between "Fsin, Fsout" in this table and "input clock, output clock" in Figure 15-4.Could you let me know it?

A2.Those values are  flowing through different processing branches and different setups of the pre-filter,

That ASRC can be used to handle different rate conversion requirements.

[Q3]Please see ATSC bit in chapter 15.7.1.Could you let me know how ASRC decide a sampling rate for input / output if ATSC is set?

A3. In case the ATSA,ATSB,ATSC bit of ASRCTR is enabled, the pre/post filter settings are determined automatically

Hope it helps

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Bio_TICFSL
NXP TechSupport
NXP TechSupport

1) Is my understanding correct?

A1. The main function of ARSC is Converting the sampling rate of a signal associated  to an input clock into a signal associated to a different output clock. Clocks shall be physically available e.g. Different clock sources, with different dividers

SSI/ESAI      --- normally divide 64

SPDIF(Rx)    --- normally divide 128

[Q2]Please see Table 15-7.I want to confirm correspondence between "Fsin, Fsout" in this table and "input clock, output clock" in Figure 15-4.Could you let me know it?

A2.Those values are  flowing through different processing branches and different setups of the pre-filter,

That ASRC can be used to handle different rate conversion requirements.

[Q3]Please see ATSC bit in chapter 15.7.1.Could you let me know how ASRC decide a sampling rate for input / output if ATSC is set?

A3. In case the ATSA,ATSB,ATSC bit of ASRCTR is enabled, the pre/post filter settings are determined automatically

Hope it helps

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