Configuring imx6 solo JTAG pin options using the device tree

[scottwarner]

I'm working on an imx6 solo based custom board that used sabresd as a reference.  We are currently using the dora 3.10.9_alpha release.  I'm trying to set pin options for the following JTAG pins:

20E_0614 (IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD)

20E_0618 (IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK)

20E_061C (IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI)

20E_0620  (IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO)

20E_0624  (IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS)

20E_0628  (IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB)

I didn't see any definitions for these pins in imx6dl-pinfunc.h so I tried adding them (imx6dl-pinfunc.h, .dtsi, and in the pinctrl-imx6dl.c files), but when the system boots I get the following messages for the pins:

imx6dl-pinctrl 20e0000.iomuxc: failed to get pin(389) name

imx6dl-pinctrl 20e0000.iomuxc: failed to get pin(390) name

imx6dl-pinctrl 20e0000.iomuxc: failed to get pin(391) name

imx6dl-pinctrl 20e0000.iomuxc: failed to get pin(392) name

imx6dl-pinctrl 20e0000.iomuxc: failed to get pin(393) name

imx6dl-pinctrl 20e0000.iomuxc: failed to get pin(394) name

pinconfig core: failed to register map default (47): no group/pin given

imx6dl-pinctrl 20e0000.iomuxc: initialized IMX pinctrl driver

I'm not sure if I'm still missing something that needs to be added or if these pins are handled different because they don't have mux options.

Thanks,

Scott

[AnsonHuang]

Hi, Scott

     Can you paste the whole patch you add? Maybe I can help after looking into your patch.

[scottwarner]

Hi Yongcai,

The original reply had the patch as an attachment, not sure if that worked so I'll try it this way:

Index: arch/arm/boot/dts/imx6qdl-mohawk-gpios.dtsi

===================================================================

--- arch/arm/boot/dts/imx6qdl-mohawk-gpios.dtsi (revision 6370)

+++ arch/arm/boot/dts/imx6qdl-mohawk-gpios.dtsi (working copy)

@@ -631,18 +631,17 @@

  MX6QDL_PAD_GPIO_9__SD1_WP MX6DL_USDHC_PAD_CTRL

  /* RGMIII Interface (GIGE) */

- /*MXDL_PAD_CTL_GRP_DDR_TYPE_RGMIII__1P2V_IO (PAD_CTL_RGMIII_1P2V)

- *MXDL_PAD_CTL_GRP_RGMIII_TERM__DISABLE 0x0

- */

+ MX6QDL_PAD_CTL_GRP_DDR_TYPE_RGMIII__1P2V_IO (PAD_CTL_RGMIII_1P2V)

+ MX6QDL_PAD_CTL_GRP_RGMIII_TERM__DISABLE 0x0

+

  /* JTAG */

- /*MX6DL_PAD_JTAG_MOD__SJC_MOD (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

- *MX6DL_PAD_JTAG_TCK__SJC_TCK (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

- *MX6DL_PAD_JTAG_TDI__SJC_TDI (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

- *MX6DL_PAD_JTAG_TDO__SJC_TDO (PAD_CTL_PUS_100K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

- *MX6DL_PAD_JTAG_TMS__SJC_TMS (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

- *MX6DL_PAD_JTAG_TRSTB__SJC_TRSTB (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

- */

+ MX6QDL_PAD_JTAG_MOD__SJC_MOD (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

+ MX6QDL_PAD_JTAG_TCK__SJC_TCK (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

+ MX6QDL_PAD_JTAG_TDI__SJC_TDI (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

+ MX6QDL_PAD_JTAG_TDO__SJC_TDO (PAD_CTL_PUS_100K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

+ MX6QDL_PAD_JTAG_TMS__SJC_TMS (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

+ MX6QDL_PAD_JTAG_TRSTB__SJC_TRSTB (PAD_CTL_PUS_47K_UP|PAD_CTL_PUE|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_48ohm|PAD_CTL_SRE_FAST)

  /* Mohawk GPIOs configured starting here */

  MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 (MX6DL_GPIO_OUTPUT_CTL)

Index: arch/arm/boot/dts/imx6dl-mohawk-pinfunc.h

===================================================================

--- arch/arm/boot/dts/imx6dl-mohawk-pinfunc.h (revision 6316)

+++ arch/arm/boot/dts/imx6dl-mohawk-pinfunc.h (working copy)

@@ -1122,14 +1122,14 @@

#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0

/* Exported from Old BSP */

-#define MXDL_PAD_CTL_GRP_DDR_TYPE_RGMIII__1P2V_IO 0x0 0x0768 0x0 0x0 0x0

-#define MXDL_PAD_CTL_GRP_RGMIII_TERM__DISABLE 0x0 0x0788 0x0 0x0 0x0

-#define MX6DL_PAD_JTAG_MOD__SJC_MOD 0x0 0x0614 0x0000 0 0

-#define MX6DL_PAD_JTAG_TCK__SJC_TCK 0x0 0x0618 0x0000 0 0

-#define MX6DL_PAD_JTAG_TDI__SJC_TDI 0x0 0x061C 0x0000 0 0

-#define MX6DL_PAD_JTAG_TDO__SJC_TDO 0x0 0x0620 0x0000 0 0

-#define MX6DL_PAD_JTAG_TMS__SJC_TMS 0x0 0x0624 0x0000 0 0

-#define MX6DL_PAD_JTAG_TRSTB__SJC_TRSTB 0x0 0x0628 0x0000 0 0

+#define MX6QDL_PAD_CTL_GRP_DDR_TYPE_RGMIII__1P2V_IO 0x0 0x0768 0x0 0x0 0x0

+#define MX6QDL_PAD_CTL_GRP_RGMIII_TERM__DISABLE 0x0 0x0788 0x0 0x0 0x0

+#define MX6QDL_PAD_JTAG_MOD__SJC_MOD 0x0 0x614 0x0000 0 0

+#define MX6QDL_PAD_JTAG_TCK__SJC_TCK 0x0 0x618 0x0000 0 0

+#define MX6QDL_PAD_JTAG_TDI__SJC_TDI 0x0 0x61C 0x0000 0 0

+#define MX6QDL_PAD_JTAG_TDO__SJC_TDO 0x0 0x620 0x0000 0 0

+#define MX6QDL_PAD_JTAG_TMS__SJC_TMS 0x0 0x624 0x0000 0 0

+#define MX6QDL_PAD_JTAG_TRSTB__SJC_TRSTB 0x0 0x628 0x0000 0 0

#endif /* __DTS_IMX6DL_MOHAWK_PINFUNC_H */

Index: drivers/pinctrl/pinctrl-imx6dl.c

===================================================================

--- drivers/pinctrl/pinctrl-imx6dl.c (revision 6311)

+++ drivers/pinctrl/pinctrl-imx6dl.c (working copy)

@@ -233,6 +233,14 @@

  MX6DL_PAD_SD4_DAT5 = 213,

  MX6DL_PAD_SD4_DAT6 = 214,

  MX6DL_PAD_SD4_DAT7 = 215,

+ MX6DL_PAD_CTL_GRP_DDR_TYPE_RGMIII = 216,

+ MX6DL_PAD_CTL_GRP_RGMIII_TERM = 217,

+ MX6DL_PAD_JTAG_MOD = 218,

+ MX6DL_PAD_JTAG_TCK = 219,

+ MX6DL_PAD_JTAG_TDI = 220,

+ MX6DL_PAD_JTAG_TDO = 221,

+ MX6DL_PAD_JTAG_TMS = 222,

+ MX6DL_PAD_JTAG_TRSTB = 223,

};

/* Pad names for the pinmux subsystem */

@@ -453,6 +461,14 @@

  IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5),

  IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6),

  IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),

+ IMX_PINCTRL_PIN(MX6DL_PAD_CTL_GRP_DDR_TYPE_RGMIII),

+ IMX_PINCTRL_PIN(MX6DL_PAD_CTL_GRP_RGMIII_TERM),

+ IMX_PINCTRL_PIN(MX6DL_PAD_JTAG_MOD),

+ IMX_PINCTRL_PIN(MX6DL_PAD_JTAG_TCK),

+ IMX_PINCTRL_PIN(MX6DL_PAD_JTAG_TDI),

+ IMX_PINCTRL_PIN(MX6DL_PAD_JTAG_TDO),

+ IMX_PINCTRL_PIN(MX6DL_PAD_JTAG_TMS),

+ IMX_PINCTRL_PIN(MX6DL_PAD_JTAG_TRSTB),

};

static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {

[AnsonHuang · Accepted solution]

Hi, Scott

     I think the root cause is that the definition you add for JTAG pin in arch/arm/boot/dts/imx6dl-mohawk-pinfunc.h, the first column must equal to the pinctrl driver's enum, for example, MX6DL_PAD_JTAG_MOD is defined to 218, then the definition in arch/arm/boot/dts/imx6dl-mohawk-pinfunc.h should be: #define MX6QDL_PAD_JTAG_MOD__SJC_MOD 0x368 0x614 0x0000 0 0, 0x368 = 218 * 4; Below is my patch for you, if it is working, please check the correct answer and close this topic, thanks!

diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h

index b81a7a4..c8aafcc 100644

--- a/arch/arm/boot/dts/imx6dl-pinfunc.h

+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h

@@ -1085,5 +1085,6 @@

#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA          0x35c 0x744 0x000 0x2 0x0

#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA          0x35c 0x744 0x904 0x2 0x7

#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0

+#define MX6QDL_PAD_JTAG                             0x360 0x614 0x000 0x0 0x0

#endif /* __DTS_IMX6DL_PINFUNC_H */

diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts

index 5713c71..76c3001 100644

--- a/arch/arm/boot/dts/imx6dl-sabresd.dts

+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts

@@ -104,6 +104,7 @@

                                MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000

                                MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000

                                MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000

+                               MX6QDL_PAD_JTAG               0x00003060

                                /* elan touch */

                                MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000

                                MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000

diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/pinctrl-imx6dl.c

index a76b724..0e39ab5 100644

--- a/drivers/pinctrl/pinctrl-imx6dl.c

+++ b/drivers/pinctrl/pinctrl-imx6dl.c

@@ -233,6 +233,7 @@ enum imx6dl_pads {

        MX6DL_PAD_SD4_DAT5 = 213,

        MX6DL_PAD_SD4_DAT6 = 214,

        MX6DL_PAD_SD4_DAT7 = 215,

+       MX6DL_PAD_JTAG = 216,

};

/* Pad names for the pinmux subsystem */

@@ -453,6 +454,7 @@ static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {

        IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5),

        IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6),

        IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),

+       IMX_PINCTRL_PIN(MX6DL_PAD_JTAG),

};

[scottwarner]

That's the piece I was missing, works great now, thanks for your help!

Scott

[scottwarner]

Hi Yongcai,

Here's a little background on the files:

imx6dl-mohawk-pinfunc.h is our board specfic version of imx6dl-pinfunc.h

imx6qdl-mohawk-gpios.dtsi is our board specific version of imx6qdl-sabresd.dtsi the pins were added to the hog group under the iomux node.

Thanks for taking a look at this,

Scott