Hello,
we have a problem with the lpspi6 clock on the i.MX 93. When we measure the clock signal with an oscilloscope, we can see that the high-level phase and low-level phase have different lengths. The low-level takes about 66% of the period, and the high-level only 33% of the period (see attached image 'SPI6_QuickPrint60.png').
We observed that behaviour with NXP BSP version "6.6.52_2.2.0". We measured the lpspi6 clock also with the older BSP version "6.1.55_2.2.0". With that older version we see that the clock signal behaves as we would expect it (50% high and 50% low).
Unfurtunately, with that wrong duty-cycle of version "6.6.52_2.2.0" we miss the limits of the spec of the connected SPI slave.
Find below the snippet from our DTS that enables/configures the lpspi6:
// ...
&lpspi6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi6>;
cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
/* TPM */
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
// ...
pinctrl_lpspi6: lpspi6grp {
fsl,pins = <
MX93_PAD_GPIO_IO00__GPIO2_IO00 0x3fe
MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe
MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe
MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe
>;
};
// ...
Do you have any idea which impact the software can have to the duty-cycle of the lpspi6 clock?
Do you have any idea how we can narrow down the problem?
Thanks,
Christoph
