Clock Sharing Feasibility for "MCIMX6Q6AVT10AD"

[arif_kanganolli]

Hello,

Greetings,

I am using MCIMX6Q6AVT10AD on my design, i have four DDR3L( MT41K256M16TW-107 AIT:P TR) chips interfacing with i.MX6.

I am using CLK0 i.e DRAM_SDCLK_0 for all the four chips and i have left CLK1 Not connected.

Kindly provide your valuable feedback on this, whether this is the the right way or no??

Thank You

Regards,

Arif

[weidong_sun]

Hello Arif,

In theory, four DDR3L chips have no problem using the same clock. However, this usage will make PCB design more difficult, because it is difficult to do impedance matching well. Therefore, in DDR circuit design, we strongly recommend that customers refer to our EVK board.

Have a nice day!

Best Regards,

Weidong

[arif_kanganolli]

Dear Weidong,

Thank you for your valuable feedback.

We are facing EMI issues in our REV A board (We have referred SABRE D EVK board)and we are suspecting this might be because using SDCLK_0  and SDCLK_1 both i.e. DDR (CHIP1 and CHIP2) are connected to SDCLK_0 & DDR (CHIP3 and CHIP4) are connected to SDCLK_1.

Kindly provide your suggestions and feedback for the same.

Note: Our concern is EMI failures.

Thank You.

Regards,

Arif

[weidong_sun]

Hi Arif,

   The followong links on SDCLK0/1 is recommended to you, refer to them, please!

--Difference of DRAM_SDCLK in i.MX6 

--About Clock Delay Calibration of DDR3 in i.MX6DQ. 

In addition,

We have provided DDR stress tool for customer, see the document, please!

---https://community.nxp.com/docs/DOC-105652 

Have a nice day!

BR,

Weidong