Clock Gating Unsuccessful in WAIT mode

[adamgarrison]

I’m trying to configure the device to gate several clocks when it goes into WAIT mode from a WFI instruction.  From my testing it appears that the clocks are not automatically turning off in WAIT mode, and I can’t figure out why.  I have verified that it is getting into WAIT mode, and the CPU stops executing instructions.  Do you know of anything that would prevent clocks from gating even though the device is in a WAIT state?  This is a step to reduce power.

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[igorpadykov]

Hi Adam

what clock had you checked and what environment?

It may be recommended to check that on bare-metal tests SDK

i.MX 6Series Platform SDK  Bare-metal SDK for the i.MX 6

power_modes_test.c, also there is  simple gpt test (gpt.c).

Note, for example linux uses gpt as system timer, also it uses

24MHz clock which is not gated by CCGR registers

ipg_clk_root by CCGR1[CG10],

ipg_clk_highfreq (perclk_clk_root) by CCGR1[CG11]

Table 18-3 IMX6DQRM

Best regards

igor

[adamgarrison]

what clock had you checked and what environment?

  I’m running the QNX 6.6 OS.  If any of your contacts knows of any particular gotchas with this OS, that would be great to know.  I’ve checked many of the clocks. The two most important are EPIT2 and EPIT1, which should be gated by CCGR1(CG7 and CG6).  That bare metal test on the SDK looks exactly like something I want to try out. 

I have the CCGR bits set to gate the clocks in WAIT mode, but nothing turns off.  It almost feels like there is some mystery bit in some other register that also needs to be set.

Thank you,

Adam

[igorpadykov]

EPIT has special WAITEN bit in Control register (EPITx_CR),

enablng the operation of the EPIT during wait mode.

Best regards

igor