Clarify the choice of ECC strength in gpmi-nand driver

[jupiter_hce]

Hi igorpadykov ,

You responded in a thread Choice of ECC strength in gpmi-nand driver  that the NAND should use lower strength ECC (4 bit) to avoid unnecessary overheads related to bigger ecc calculations. Is it correct that the default ECC in gpmi-nand driver is 8 bit? Should it be change to lower 4 bit ECC?

You also responded my question in another thread about Flash u-boot-nand.imx to NAND based on (customized) imx6ull-14x14-evk, that nxp does not support such operations in uboot, in other words, we cannot use u-boot to flash u-boot-solar.imx-nand to NAND, it has to be done in Linux using kobs.

What is the correct ECC for kobs calling ROM process 8 bit? If I have to use 8 bit ECC for flashing u-boot-solar.imx-nand to NAND, I have to build two DTBs, one for booting ramdisk to flash u-boot-solar.imx-nand, and another for lower ECC DTB for NAND driver, right?

Thank you.

Kind regards,

jupiter

[igorpadykov]

Hi Jupiter

> Is it correct that the default ECC in gpmi-nand driver is 8 bit?

in general this depends on linux release which used in the case. Suggest

to check driver sources using linux documentation on

i.MX Software and Development Tools | NXP 

>nxp does not support such operations in uboot, in other words, we cannot use u-boot to

>flash u-boot-solar.imx-nand to NAND, it has to be done in Linux using kobs.

right, nxp uboot does not support this,

>What is the correct ECC for kobs calling ROM process 8 bit?..

I do not think that kobs is calling ROM. In general during boot NAND FCB

has ecc parameters described in Table 8-11. Flash control block structure

Table 8-11. Flash control block structure  i.MX 6ULL Applications Processor Reference Manual

Best regards
igor
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[jupiter_hce]

> I do not think that kobs is calling ROM.

Does that mean there is no ECC requirement for kobs flashed my u-boot.imx6ull-nand to NAND? If so, I should use any ECC setting either 4 bit or 8 bit, right?

> In general during boot NAND FCB has ecc parameters described in Table 8-11.

> Flash control block structure Table 8-11. Flash control block structure

Could you point me which document for the Table 8-11? Also which document for kobs requirements you mentioned it would not call ROM?

Thank you.

Kind regards,

jupiter

[igorpadykov]

> I should use any ECC setting either 4 bit or 8 bit, right?

you should look at nand datasheet for its ecc requirements.

>Could you point me which document for the Table 8-11?

i.MX 6ULL Applications Processor Reference Manual

>Also which document for kobs requirements you mentioned it would not call ROM?

please provide document where you found that kobs calls ROM.

Best regards
igor

[jupiter_hce]

Thanks igor for your kindly response.

> please provide document where you found that kobs calls ROM.

Sorry, I was advertised by the hardware contractor who is the one controlled our NXP component supply chain, but he did not provide me the document. Sorry I have to find all documents and information from you and this forum.

According to the hardware contract advice that ECC strength bit for using kobs to flash u-boot-nand.imx should be 8 bits where the ECC for NAND should be 4 bit, I am not sure if the hardware contractor's advice from NXP official channel or not, if he is wrong about kobs calling ROM, he could be wrong about the ECC strength bit for running kobs to flash u-boot-nand.imx as well, sorry for nagging you to clarify if there is a requirement of ECC strength bit for lashing u-boot-nand.imx to i.MX6ULZ NAND or not. If the hardware contractor is wrong, I should use 4bit ECC to flash the u-boot-nand.imx.

l also looked at your comments in another thread  i.MX6 and NAND flash H27UBG8T2CTR 

"as log states no, this flash can not be supported by the i.MX6 NAND/BCH controller.

It requires 44bit ecc for covering both data and metadata, example of such calculations

can be found in i.MX6DQ Reference Manual 17.2.3 Determining the ECC layout for a device.

Regarding lower ECC strength, seems this is not good since it can affect NAND reliability

and can not be guaranteed by datasheet."

If 44bit ecc for covering both data and metadata for i.MX6DQ, does it also apply for i.MX6ULZ? Did you comment of "Regarding lower ECC strength, seems this is not good since it can affect NAND reliability" also apply for i.MX6ULZ as well alluded I should use 8bit ECC for NAND?

Thank you.

Kind regards.

[igorpadykov]

Hi Jupiter

>If 44bit ecc for covering both data and metadata for i.MX6DQ, does it also apply for i.MX6ULZ? 

for i.MX6ULZ it is necessary to use i.MX 6ULZ Applications Processor Reference Manual

Chapter 16 40-BIT Correcting ECC Accelerator (BCH).

Best regards
igor