Clarifications about usage of fec2 reference clock on iMX7D

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Clarifications about usage of fec2 reference clock on iMX7D

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msalvinik
Contributor II

Hi all,

I have some questions about how to connect the fec2 MAC to a PHY controller on iMX7D, specifically the reference clock signal.

In my configuration I have an external oscillator driving the 50MHz reference clock. The MX7D_PAD_EPDC_BDR0 pad is connected to the REFCLK pin on PHY, ant the oscillator output is connected to this line.

In IOMUXC_GPR_GPR1 register there are 4 bits that controls:

- the clock selection for eth1 and eth2 (bits 13 and 14): if 0, interface uses the internal clock, if 1 the interface uses clock coming from ENETx_TX_CLK pin

- the output of the clock on pin ENETx_TX_CLK (bits 17 and 18), when ALT1 (ENET_REF_CLKx function) is selected on the pinmux for that pin

Here comes the first question: ENET2_TX_CLK pad does NOT exist on IOMUX so:

1) on what pad the output selection is set by the IOMUXC_GPR_GPR1 bit 18?

Seems that this bit is useful only for ETH1, when the ETH1_TX_CLK pad (SW_MUX_CTL_PAD_ENET1_TX_CLK) is used to generate/receive external clock. Seems that for ENET2 this bit is totally unuseful.

If I understand correctly, muxing the MX7D_PAD_EPDC_BDR0 pad to CCM_ENET_REF_CLK2 (MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2, alt3) connects the internal clock for enet2 to this pad, outputting it. So, if I set IOMUXC_GPR_GPR1 bit 14 to 0, excluding the external oscillator I can drive an external PHY and the MAC with the internal generated clock. The same result if I mux the pad to ENET2_TX_CLK (ALT2), the clock is outputted.

Then the subsequent questions:

2) if I set the bit 14 to 1 to get the external clock coming on ENET2_TX_CLK, how I can drive an external oscillator clock on the ENET2_TX_CLK to have clock source on it? using ALT2 for MX7D_PAD_EPDC_BDR0?

3) if the previous answer is yes, the ALT2 mux for pad MX7D_PAD_EPDC_BDR0 enables both input and output on the pad? Or I have to set the SION bit to get the input?

Seems that using MX7D_PAD_EPDC_BDR0 I can ONLY output the clock, not get it from external.

Thanks in advance, regards

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2 Replies

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art
NXP Employee
NXP Employee

The ENETx_TX_CLK signal is only functional in the MII interface mode, and, according to the MII specification, always operates as input (there is a typo in the Table 11-1 of the i.MX7Dual Reference Manual document, indicating this signal as output). And you are right in that the ENET2_TX_CLK signal is multiplexed on the EPDC_BDR0 pad as ALT2 IOMUX mode.

Best Regards,
Artur

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788 Views
msalvinik
Contributor II

Hi all,

no updates about this question?

Thanks in advance, regards

Mauro

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