Clarification of GPIO1 dedicated interrupts -- overlap with combination interrupt.

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Clarification of GPIO1 dedicated interrupts -- overlap with combination interrupt.

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AndrewDeAngelis
Contributor II

Hello. this is for a project with the IMX7D processor.

 

I have a question about the GPIO1[7:0] dedicated interrupts and the way they overlap with the shared GPIO1[15:0] interrupt -- Is it possible for an interrupt on GPIO[2] to show up on the dedicated interrupt but not trigger the combination interrupt? Say by masking that bit in the appropriate GPIO_IMR? Or will masking the pin in the IMR not only stop it from triggering the combo GPIO1[15:0] interrupt, but stop it from triggering the dedicated GPIO1[2] interrupt as well? Are the dedicated GPIO1[7:0] interrupts affected by the edge/level settings in the ICR registerm or do those only affect the shared GPIO1[15:0] interrupt?

 

Here is an illustrative situation. We have an interrupt on GPIO1[2] that should interrupt the A7 Core1, but not the A7 Core0. However there are interrupts on GPIO1[13:12] that must be serviced by A7 Core0. We don't want the ISR for shared GPIO1[15:0] running on A7 Core0 to be triggered by a GPIO2 falling edge, because it will happen very often, and even if the ISR is short, will affect performance. But, on a GPIO2 falling edge, we do want the A7 Core1 ISR for dedicated GPIO1[2] "Active HIGH INT2 from GPIO" interrupt to be run.

 

Does this change if A7Core 1 core was the M4 Core instead?

 

Thank you,

 

Andrew

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igorpadykov
NXP Employee
NXP Employee

>Are the interrupts only for GPIO active high? 

no.

IRQs for GPIO1[7:0] (active high, low, rising/falling edges) can be configured with GPIO1_ICR1 fields.

Best regards
igor

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AndrewDeAngelis
Contributor II

Thank you igor. Are you saying that setting GPIO_IMR bit will mask the dedicated GPIO1[2] interrupt on IRQ61 as well as the masking GPIO1[2] as a source to the combined interrupt on IRQ64?

If we set the GPIO_ICR to falling edge trigger, will this make falling edge on GPIO1[2] trigger IRQ61 if IMP bit is not set?

Thank you.

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igorpadykov
NXP Employee
NXP Employee

Hi Andrew

>Are you saying that setting GPIO_IMR bit will mask the dedicated GPIO1[2] interrupt on IRQ61 as well

>as the masking GPIO1[2] as a source to the combined interrupt on IRQ64?

yes

>

If we set the GPIO_ICR to falling edge trigger, will this make falling edge on GPIO1[2] trigger IRQ61 if IMP bit is not set?

sorry could not understand, could you rephrase it.


Best regards
igor

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AndrewDeAngelis
Contributor II

Yes, I will rephrase:

for these IRQs, dedidcated IRQs for GPIO1[7:0], 

56 GPIO1 Active HIGH Interrupt from INT7 from GPIO
57 GPIO1 Active HIGH Interrupt from INT6 from GPIO
58 GPIO1 Active HIGH Interrupt from INT5 from GPIO
59 GPIO1 Active HIGH Interrupt from INT4 from GPIO
60 GPIO1 Active HIGH Interrupt from INT3 from GPIO
61 GPIO1 Active HIGH Interrupt from INT2 from GPIO
62 GPIO1 Active HIGH Interrupt from INT1 from GPIO
63 GPIO1 Active HIGH Interrupt from INT0 from GPIO

Are the interrupts only for GPIO active high? Or could they be configured to trigger on active low, rising edge, falling edge by programming GPIO1_ICR1 fields ICR[7:0] ?

Thank you.

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igorpadykov
NXP Employee
NXP Employee

>Are the interrupts only for GPIO active high? 

no.

IRQs for GPIO1[7:0] (active high, low, rising/falling edges) can be configured with GPIO1_ICR1 fields.

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi Andrew

>Is it possible for an interrupt on GPIO[2] to show up on the dedicated interrupt but
>not trigger the combination interrupt?

unfortunately not. Appropriate GPIO_IMR has not masking functionality for that.

Best regards
igor
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