Change Slew Rate of DDR3 for i.MX6ULL

[chauhan_pandura]

Hello All,

For one of our boards, it is required to change the slew rate of Clock, Address and Data lines of DDR3 memory connected with i.MX6ULL processor. We have gone through datasheets, reference manuals and web-links for this, but cannot find anything for the same.

Do anyone have idea about how to do this - change slew rate of DDR3 signals connected with i.MX6ULL?

I have found one link ( https://www.nxp.com/docs/en/engineering-bulletin/EB828.pdf ), section #4 which is about VIX measurement. I feel this may impact to slew rate behavior, but I am not sure.

Kindly guide or give a hint.

Thanks and Regards.

[igorpadykov]

Hi chauhan_pandura

there is no special slew rate setting for ddr signals, as for example SRE,

it can be changed using drive strength DSE field.

Best regards
igor

[chauhan_pandura]

Thanks igor.

Let me tell you (and all), the main reason to change slew rate is to reduce radiation from DDR3 signal lines.

So, can drive strength change radiation?

Another query, can VIX (or ZQ) setting affect slew rate? (I am asking this as per link I shared in my first post.)

Regards.

[igorpadykov]

Hi chauhan_pandura

yes drive strength can change radiation, also EMI issues may be caused by board

layout, recommended to follow ddr layout guidelines provided in

Hardware Development Guide for the i.MX 6ULL Applications Processor

Best regards
igor

[igorpadykov]

Hi chauhan_pandura

yes drive strength can change radiation, also EMI issues may be caused by board

layout, recommended to follow ddr layout guidelines provided in

Hardware Development Guide for the i.MX 6ULL Applications Processor

Best regards
igor

[chauhan_pandura]

Thanks Igor.

I have checked Drive strength bit for DRAM lines in Reference manual of i.mx6 and found that For Address lines, it is Read-only bit along with many other lines!

We can change the Drive Strength for below lines:

- DQM0, DQM1, RAS_B, CAS_B, ODT0, ODT1, SDCLK0_P, SDQS0_P, SDQS1_P and RESET.

Kindly confirm this.

Also, is there any way to change Drive strength of Clock, Address lines and Data Lines?

Kindly confirm that As per Section #4 of https://www.nxp.com/docs/en/engineering-bulletin/EB828.pdf

link, changing the value of 0x021B0890 register changes slew rate of a signal?

Regards.

[igorpadykov]

drive strength can be changed using IOMUXC_SW_PAD_CTL_GRP_ADDDS,

SW_PAD_CTL_GRP_B0DS SW GRP, SW_PAD_CTL_GRP_CTLDS SW GRP registers.

VIX (described in EB828) does not affect drive strength.

Best regards
igor

[chauhan_pandura]

Hello Igor.

Once again thank you for your quick reply.

My further query is:

Current value of Drive strength for all signals is R0/3 (where R0 = 240 Ohm). So, now to reduce radiation by some margin, should we increase Resistance of a pad ( in which case Drive strength parameter value = R0/2 or R0 ) or decrease the Resistance ( in which case Drive strength parameter value = R0/4, R0/5, R0/6 or R0/7)?

NOTE: I have searched for relation between Drive strength and radiation, but could not find any link.

Can VIX (ZQ) setting affect slew-rate?

Regards.

[igorpadykov]

drive strength value should be find experimentally.

If it is not possible to find optimal values, board relayout is needed.

>Can VIX (ZQ) setting affect slew-rate?

not

Best regards
igor