Change Data Enable(DRDY) from PIN15 to PIN04 for interfacing a Parallel RGB LCD display to iMX6D.

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Change Data Enable(DRDY) from PIN15 to PIN04 for interfacing a Parallel RGB LCD display to iMX6D.

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zaheerm
Contributor I

The reference iMX6Q reference platform has DI0_PIN15 configured as the DATA ENABLE line for interfacing a parallel RGB LCD.

Our custom hardware has the DE line on DI0_PIN04, is it possible to configure the DE line to DI0_PIN4?

From the uboot sources, in the file 'driver/video/ipu_disp.c', there is an following function which I believe is used to configure the DI0_PIN15 as the DE:

ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);

In the above function, the register 'IPUx_DI0_DW_GEN_i' is being configured for DI0_PIN15. I don't see the way to configure PIN04 here.

Pl. let me know if i can configure the DI0_PIN04 as DE?

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qiang_li-mpu_se
NXP Employee
NXP Employee

Based on L3.0.35_4.1.0 GA BSP, I had succussfully generated Data Enable signal from DI0_PIN04, from measurement, the waveform is fully same as the DI0_PIN15 (Pin04&Pin15 waveform.jpg).

The attached is the kernel patch and the patched source code, you can select one to use. The patch was verified on iMX6Q SabreSD board with the CLAA WVGA panel.

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qiang_li-mpu_se
NXP Employee
NXP Employee

You can generate timing signal output from DI0_PIN04 and connect it to the LCD to simulate the data enable signal, but the real Data Enable signal still outputs from PIN15.


From my point of view, the simulated signal output on DI0_PIN04 can be same as real Data Enable signal by programing the DI counter related registers.

Since the DI counter 4 had already been used in current BSP, it needs modify all IPU DI and DC code to free it for DI_PIN4, I don't have such reference code.


The followed is an example to use DI_PIN6 as Data Enable, in ipu_disp.c:

  _ipu_di_sync_config(ipu, disp,
     6,   //DI_COUNTER 6
     1 - 1,  DI_SYNC_HSYNC,   // The signal referenced to HSYNC, period is 1 HSYNC
     1, DI_SYNC_CLK,  // Offset, the signal will appear after 1 pixel clocks each time
     1, // The signal appears once each time.
     DI_SYNC_HSYNC,  //  The signal restarts with each HSYNC.
     1,  // The signal needs be output from DI_PIN6
     DI_SYNC_NONE,
     DI_SYNC_CLK, 0, (width) * 2);  // The signal keeps high in width pixel clocks.


The Offset, up, down setting can be used to adjust the DI_PIN06 waveform.

For how to re-assign the DI counter and DI PINs, you can reference to this link:

https://community.freescale.com/thread/279078

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zaheerm
Contributor I

Followed the instructions and added the Counter-4 for DRDY/DE. Moved existing counter-4 to 5 and counter-5 to 6. The value of DI0 Sync Wave Gen 4 Register 0 (IPU1_DI0_SW_GEN0_4) is 0x30009. Is it a correct value?

However I am still not able to generate a DE signal.

Its difficult to identify the registers associated with DI and DC which have been programmed for DI_PIN4 as active data.

Request the community to provide details on configuring the pin-4 as DE.

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qiang_li-mpu_se
NXP Employee
NXP Employee

Attached is an sample code based on 3.0.35_4.1.0 GA BSP.

I haven't measured the PIN04 signal, maybe you need adjust it for your panel, this modification can make the LVDS panel working on iMX6 sabresd board, so the modification is OK.

By the way, you should set the IOMUX for PIN04 in your board file, such as MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4.

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zaheerm
Contributor I

Thanks for providing the code changes, I made similar changes in the uboot code and I am still not able to see the DE generated.

The IOMUX configuration for the pad is IPU1_DI0_PIN4.

I have attached the source file, request you to have a look and pl. recommend. You had earlier mentioned that I need to modify the DI and DC registers to free PIN-4 of its earlier functionality. I didn't see that change in the the file you sent me. Is that change needed?

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qiang_li-mpu_se
NXP Employee
NXP Employee

Today, I do some basic tuning for the PIN04 signal, with the followed DI setting code:

  _ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_INT_HSYNC,

    (h_sync_width + h_start_width), DI_SYNC_CLK, 0,

    DI_SYNC_NONE, 1, DI_SYNC_NONE,

    DI_SYNC_CLK, 0, width * 2);

I had got the attached jpg waveform. The blue is the real Data Enable signal output from DI_PIN15, the yellow is the current DI_PIN04 signal, from the picture, we can see the two signals are in same frequency, but the pulse width and offset are not same, they can be tuned by adjusting the offset, up and down setting of DI counter 4 code.

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zaheerm
Contributor I

what is the value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04?

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qiang_li-mpu_se
NXP Employee
NXP Employee

Based on L3.0.35_4.1.0 GA BSP, I had succussfully generated Data Enable signal from DI0_PIN04, from measurement, the waveform is fully same as the DI0_PIN15 (Pin04&Pin15 waveform.jpg).

The attached is the kernel patch and the patched source code, you can select one to use. The patch was verified on iMX6Q SabreSD board with the CLAA WVGA panel.

View solution in original post

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zaheerm
Contributor I

Thanks Qiang, for providing the detailed info. I was earlier trying to enable the LCD in uboot, but was not successful.

However when I made the same changes to the kernel, I am able to see the DE at PIN-04.

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qiang_li-mpu_se
NXP Employee
NXP Employee

The macro "MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4" had included the PAD_CTL setting.

#define  MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4                        (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))

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Wlodek_D_
Senior Contributor II

Hello,

Thank you for your post, however please consider moving it to the right community place (e.g. i.MX Community ) to get it visible for active members.

For details please see general advice Where to post a Discussion?

Thank you for using Freescale Community.

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