Can not control GPIO after set it to pull high.

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Can not control GPIO after set it to pull high.

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wangtsungli
Contributor IV

Hi Community,

I'm working on i.MX6 Quad sabre-SD platform and build Android 6 as my image.

I'm trying to control GPIO in u-boot.

According to my customize u-boot, I modify bootload/bootloader/u-boot/board/freescale/FX100/FX100.c like below.

.

.

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#define FX_GPIO_INIT (PAD_CTL_PUS_100K_DOWN)

static void enable_lvds(struct display_info_t const *dev)
{

   

/* LVDS_PWR_ON */
imx_iomux_v3_setup_pad(MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(FX_GPIO_INIT));
/* LVDS_BL_ON */
imx_iomux_v3_setup_pad(MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(FX_GPIO_INIT));
/* PAD_SD1_DAT3 for pwm ,GPIO mode */
imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(FX_GPIO_INIT));


gpio_direction_output(BL_PWM, 0);// winmate BL pwm to low level
gpio_direction_output(LVDS_PWR_ON, 0);//winmate Frank BL pwr off
gpio_direction_output(LVDS_BL_ON, 0);// winmate frank for panel pwr seq panel pwr off


gpio_set_value(BL_PWM, 0);
gpio_set_value(LVDS_PWR_ON, 0);
gpio_set_value(LVDS_BL_ON, 0);

setup_display();

gpio_set_value(BL_PWM, 1);
gpio_set_value(LVDS_PWR_ON, 1);
gpio_set_value(LVDS_BL_ON, 1);

}

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.

.

As you can see, I tried to define FX_GPIO_INIT to change gpio to 100K PULL DOWN..

But when I set LVDS_PWR_ON to  0 and set it back to 1, it won't work.

I can not control it.

Is there any possibility that I have to set other register mode for NANDF_CS2 ?

Or what else can I do to solve this situation?

Thanks in Advanced!

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igorpadykov
NXP Employee
NXP Employee

Hi tsung

one can check if ODE (open drain) is set using jtag, or there is some external connection

to that pin, which may affect behavior, please check sect.36.4.433 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B) i.MX6DQ Reference Manual
https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf


Best regards
igor
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