Can imx8m mini mipi-csi dphy accept continuous clk from camera?

[yuefengzhu]

Hello: 

I am running into a problem when using a camera module. The camera clock lane seems running continuously without going into LP11 state. When I probe the dphy state, it gives me 0xc1, which means data lane 0 and 1 are active (it matches my lane setting), but the clock lane is in stop state.

The camera vendor claims that it can work with imx8QM. I haven't test yet. But if it is true, it will be weird to see imx8QM's dphy can handle the continous clk but imx8m mini can't. 

Is there anyone who has any ideas how imx8m mini's mipi-csi dphy works? Is there anything I can change in the kernel?  My current kernel version is 4.14.98. The imx8m mini module is from Compulab. The camera module is from allied vision. Thank you for sharing any thoughts! 

[honklee]

I guess I'm having the same issue here: Register MIPI_CSI_DPHY_STATUS transitions from
Bitfield STOPSTATEDAT 1 to 0 (which is good) but Bitfield STOPSTATECLK remains at 1, which
means: "Clock lane is in Stop State".

On the i.MX 8M the setup is working, on the i.MX 8M Mini it is not.

The MIPI CSI Host Controller differs on these two SoCs.

So I guess your vendors claim could be right if QM differs from Mini:

@NXP_0: Is the i.MX 8 QM using the same MIPI CSI Host Controller as the 8M but not as the 8M Mini?

Here my questions regarding i.MX 8M Mini CSI:

@NXP_1: The MIPI Clock (coming from the camera sensor) cannot be just turned on as a continuous clock (at least not on the i.MX 8 Mini). But what should the initialization of the MIPI Clock (coming from the camera sensor) look like so that the i.MX 8 Mini does detect it successfully and transition STOPSTATECLK from 1 to 0 (which would be good state)?

@NXP_2a: TRM of i.MX 8M Mini Register MIPI_CSI_CSIS_CLOCK_CTRL:0x32e30008 does not describe Bit 0 at all, but TRM of i.mx7 does as WCLK_SRC. Why is that?

@NXP_2b: TRM lacks description of WCLK_SRC while referencing WCLK_SRC in some places like MIPI_CSI_INTERRUPT_SOURCE_0 Bit ERR_OVER. Is this a Bug?

@NXP_2c: On i.MX 8M Mini the driver sets in Register MIPI_CSI_CSIS_CLOCK_CTRL:0x32e30008 Bit Number 0 (WCLK_SRC) to value 1, but reading value of Bit Number 0 back it is a 0. Why is that? Shouldn't it be 1?

@NXP_2d: How to configure the MIPI interface of the i.MX 8M Mini regarding the clock coming from camera sensor (external clock)?

@NXP_3a: Is MIPI PHY (described in TRM i.MX 8M Mini 13.6.10 MIPI PHY Memory Map/Register Definition) somehow related/connected to the CSI (camera interface)?

@NXP_3b: In TRM i.MX 8M Mini "13.6.10 MIPI PHY Memory Map/Register Definition" I cannot find any absolute register-Address like I do for e.g. MIPI_CSI_DPHY_STATUS = 0x32e30020. What is the absolute register address for the MIPI PHY?

[hbeij]

Hi all,

I've documented some more research on this incompatibility:

https://community.nxp.com/t5/i-MX-Processors/IMX8M-Nano-CSI-2-incompatibility/td-p/1178904

MIPI CSI-2 DPHY standard accepts both continuous and non-continuous clock. 
Older versions of DPHY on NXP chips seemed to work with both modes. However, recently the IP for DPHY blocks has changed to only allow non-continuous clock.

It needs the clk lane LP11-LP10-LP00 transition to recognize the HS transmission mode, and enable the termination resistors.

If this transition is not recognized, CLK stays in stop mode, with HS termination disabled. 

I've asked NXP for clarification, no answer.

Best bet would be to see if your sensor can be switched to non-continuous mode.

Hope this helps...

[yuefengzhu]

Thank you for your response! That's what I was worried. Hopefully, I can get some answer from the camera vendor.

[Bio_TICFSL]

Hello Zhu,

I don´t think that it will work, but all the explanation of MIPI is on the Reference manual of the board, as well the supported on the BSP is on the Linux reference manual of your BSP document, where is not included this funcionality.

Regards