I purchased i.MX8M mini EVK
The EVK I purchased has 2GB of LPDDR4 designed.
(There are also EVKs designed with DDR4)
Can I change to DDR3?
Can I design with 512MB or 1GB?
The product I am designing now does not have much work on the video side.
It is about checking the video seamlessly by connecting HD-class CAM with USB.
i.MX8 Mini supports 32/16-bit LPDDR4 (up to 1.5 GHz), DDR4-2400, and DDR3L-1600. It also supports up to 8 Gbyte DDR memory space.
DDRL can be used. Can I modify it by referring to the DDR4 design?
Please share any information I can refer to.
And is there no problem with 1GB or 512MB other than 2GB?
Yes DDR3L can be used. And there is no issue with 1GB or 512MB.
Kindly share your schematic once you are done with the interfacing.
Please refer to IMX8MMHDG: i.MX 8M Mini Hardware Developer’s Guide for DDR3L.
I will refer to IMX8MMHDG:
But I have a question
Where is the circuit diagram for reference (SCH-35104, SCH-31399)?
This is not in IMX8MMHDG: , what document?
Is the document I know different from the document you are telling me?
Please let me know
The schematic is based on DDR4 and LPDDR4. but they have also mentioned DDR3 as well. It means this reference schematic is also applicable for DDR3 signal interface as well.
Section 3.4 of IMX8MMHDG:
I referred to the document composed of DDR4 (SPF-35104) and prepared a circuit diagram for review. (The circuit diagram was attached)
Have you seen the circuit diagram I attached?
If you have seen it, please give me a comment on it
According to the document (IMX8MMHDG: i.MX 8M Mini Hardware Developer's Guide), when using DDR3L, it seems to use four DDR3L.
However, the circuit diagram using DDR4 uses two DDR4.
If there is a circuit diagram composed of DDR3L, please attach it.
Please resend me the updated schematic.
If they have used 4 DRAM for their application. If we need to use 2 DRAM based on data lines and memory density we need to connect the DQ signals and address signals.
Among the above ripples, there is a circuit diagram I attached
I want you to give me a comment on it
1. Only two DDR3Ls are used? Should I use 4?
2. Please inform the wrong part of the attached circuit diagram.
3. Please attach a reference circuit diagram written in DDR3L.
4. Is there a circuit diagram written in i.MX8MM and DDR3L?
I don't use it in DDR3L, but I will treat Parity, Ten and ACT-N as TP
The other part of the wiring of DDR3L is said to be okay, so I will start working as it is.