Can any body explain the booting sequence of i.MX6 based board from power up to running a user application

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Can any body explain the booting sequence of i.MX6 based board from power up to running a user application

7,629 Views
vipulkumar
Contributor III

5 Replies

5,351 Views
vipulkumar
Contributor III

Hi,

As per my understanding, the following sequence is followed:

The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip Boot ROM.

The Boot ROM code uses the given boot select options as well as the state of various FUSE/straps and GPIO settings to determine the boot flow behavior of the SOC.

After determining the booting media,

1. What's the next step ?

2. How does Boot ROM code read and initialize the DDR settings ?

3. How do we reach the target board or customized board u-boot ?

0 Kudos
Reply

5,351 Views
jkenney3
NXP Employee
NXP Employee

Vipul,

The high level boot flow is shown in Figure 8-1 of the MX6Dual/Quad Reference Manual.

After POR is exited the internal ROM (iROM) is entered.  It handles all boot related set up and reads the data structures, IVT and DCD, at the start of the U-Boot file to determine where U-Boot will be loaded, where U-Boot's entry point is, and how much code to load.  It also reads  and executes the DCD information and commands.  The DCD commands allow the iROM to set up DDR and some other I/O as required to get things running.  If one is using High Assurance Boot, HAB, the iROM will check the image per the HAB process flows and either start the boot process or abort the boot and drop into serial recovery, aka USB, mode.

The IVT/DCD is described in section 8.6 of the MX6Dual/Quad Reference Manual.

Note that I have U-Boot as the example here but any code could be loaded by the iROM.  This allows one to use test code or custom software as they see fit.

Jim Kenney

5,351 Views
jkenney3
NXP Employee
NXP Employee

Vipul,

You need to ask question similar to this in the i.MX community.

To answer you question please review the boot chapter in the Reference Manual for the part you are considering.  For example that would Chapter 8 in the MX6Daul/Quad Ref Man.  Figure 8-1 is a high level block diagram.

Jim Kenney

NXP FAE

5,351 Views
vipulkumar
Contributor III

Thanks for reply James T Kenny.

In TI based SITARA processor, there is the following sequence to come up the u-boot

1. RBL stage (ROM BOOT LOADER)

2. Boot ROM Code (boot mode determination)

3. SPL stage (Secondary Program Loader)

4. U-bbot stage 

But in i.MX6 based SoC (consider i.MX6SL), we use single file u-boot.imx to flash u-boot.

I want to know

1. how this single file initialize the u-boot ?

2. where u-boot.imx reads configuration for DDR from?

0 Kudos
Reply

5,351 Views
LuisCasado
NXP Employee
NXP Employee

Hi Vipul,

Check the Chapter 1 in this doc.

Luis