I tried to trace the csi function and I found it has an error in mipi_csis_irq_handler:
root@edm-g-imx8mm:/sys/kernel/debug/tracing# gst-launch-1.0 v4l2src device=/dev/video0 ! video/x-raw,width=1280,height=800 ! imxvideoconvert_g2d ! fpsdisplaysink sync=false
Setting pipeline to PAUSED ...
Pipeline is live and does not need PREROLL ...
Pipeline is PREROLLED ...
Setting pipeline to PLAYING ...
New clock: GstSystemClock
^Chandling interrupt.
Interrupt: Stopping pipeline ...
Execution ended after 0:00:00.645651000
Setting pipeline to NULL ...
Freeing pipeline ...
root@edm-g-imx8mm:/sys/kernel/debug/tracing# cat trace | less
# tracer: function_graph
#
# CPU DURATION FUNCTION CALLS
# | | | | | | |
2) | v4l2_open() {
2) | mx6s_csi_open() {
2) 1.125 us | mx6s_csi_runtime_resume();
2) | mipi_csis_s_power() {
2) | mipi_csis_runtime_resume() {
2) | mipi_csis_pm_resume() {
2) + 11.125 us | mipi_csis_clk_enable();
2) + 17.125 us | }
2) + 18.500 us | }
2) + 24.375 us | }
2) + 54.125 us | }
2) + 66.125 us | }
2) 8.625 us | v4l2_ioctl();
2) | v4l2_release() {
2) | mx6s_csi_close() {
2) | mipi_csis_s_power() {
2) | mipi_csis_runtime_suspend() {
2) | mipi_csis_pm_suspend() {
2) 1.125 us | mipi_csis_enable_interrupts.isra.0();
2) 1.500 us | mipi_csis_system_enable.isra.0();
2) 4.250 us | mipi_csis_clk_disable();
2) + 11.500 us | }
2) + 13.000 us | }
2) + 21.125 us | }
2) 0.625 us | mx6s_csi_runtime_suspend();
2) + 34.000 us | }
2) + 36.875 us | }
2) | v4l2_open() {
2) | mx6s_csi_open() {
2) 1.125 us | mx6s_csi_runtime_resume();
2) | mipi_csis_s_power() {
2) | mipi_csis_runtime_resume() {
2) | mipi_csis_pm_resume() {
2) + 11.000 us | mipi_csis_clk_enable();
2) + 16.750 us | }
2) + 18.500 us | }
2) + 23.750 us | }
2) + 57.375 us | }
2) + 68.625 us | }
2) 8.375 us | v4l2_ioctl();
2) 3.375 us | v4l2_ioctl();
2) 1.875 us | v4l2_ioctl();
2) 1.625 us | v4l2_ioctl();
2) 1.375 us | v4l2_ioctl();
2) 1.250 us | v4l2_ioctl();
2) 1.000 us | v4l2_ioctl();
2) 1.375 us | v4l2_ioctl();
2) 1.000 us | v4l2_ioctl();
2) 1.000 us | v4l2_ioctl();
2) 1.625 us | v4l2_ioctl();
2) 1.875 us | v4l2_ioctl();
3) | v4l2_ioctl() {
3) 2.500 us | mipi_csis_enum_mbus_code();
3) + 26.875 us | }
3) | v4l2_ioctl() {
3) 1.000 us | mipi_csis_enum_mbus_code();
3) 3.125 us | }
3) 3.375 us | v4l2_ioctl();
3) | v4l2_ioctl() {
3) 2.375 us | mipi_csis_enum_framesizes();
3) 7.375 us | }
3) | v4l2_ioctl() {
3) 0.875 us | mipi_csis_enum_frameintervals();
3) 3.875 us | }
3) | v4l2_ioctl() {
3) 0.750 us | mipi_csis_enum_frameintervals();
3) 2.625 us | }
3) | v4l2_ioctl() {
3) 0.875 us | mipi_csis_enum_framesizes();
3) 4.125 us | }
3) | v4l2_ioctl() {
3) 0.625 us | mipi_csis_enum_frameintervals();
3) 2.875 us | }
3) | v4l2_ioctl() {
3) 0.750 us | mipi_csis_enum_frameintervals();
3) 2.750 us | }
3) | v4l2_ioctl() {
3) 1.250 us | mipi_csis_enum_framesizes();
3) 3.750 us | }
3) | v4l2_ioctl() {
3) 4.000 us | mipi_csis_set_fmt();
3) + 22.375 us | }
3) | v4l2_ioctl() {
3) 5.250 us | mipi_csis_set_fmt();
3) + 35.000 us | }
3) | v4l2_ioctl() {
3) 1.375 us | mipi_csis_g_parm();
3) 6.125 us | }
3) 3.500 us | v4l2_ioctl();
3) 1.375 us | v4l2_ioctl();
3) 8.000 us | v4l2_ioctl();
3) 2.250 us | v4l2_ioctl();
3) 2.000 us | v4l2_ioctl();
3) 1.625 us | v4l2_ioctl();
3) 1.375 us | v4l2_ioctl();
3) 2.000 us | v4l2_ioctl();
3) # 7862.500 us | v4l2_ioctl();
3) + 15.625 us | v4l2_ioctl();
3) 2.875 us | v4l2_ioctl();
3) 1.750 us | v4l2_ioctl();
3) + 38.750 us | v4l2_ioctl();
3) + 10.250 us | v4l2_ioctl();
3) + 11.875 us | v4l2_ioctl();
3) 3.375 us | v4l2_ioctl();
3) + 13.375 us | v4l2_ioctl();
3) 3.500 us | v4l2_ioctl();
3) | v4l2_ioctl() {
3) | mipi_csis_s_stream() {
3) | mipi_csis_start_stream() {
3) 2.000 us | mipi_csis_system_enable.isra.0();
3) 1.375 us | mipi_csis_enable_interrupts.isra.0();
3) + 22.250 us | }
0) 1.250 us | } /* mipi_csis_irq_handler */
0) 1.250 us | mipi_csis_irq_handler();
0) 1.250 us | mipi_csis_irq_handler();
0) 1.125 us | mipi_csis_irq_handler();
0) 1.125 us | mipi_csis_irq_handler();
0) 1.125 us | mipi_csis_irq_handler();
...
0) 1.375 us | mipi_csis_irq_handler();
0) 1.500 us | mipi_csis_irq_handler();
0) 1.375 us | mipi_csis_irq_handler();
0) 2.125 us | mipi_csis_irq_handler();
0) 1.500 us | mipi_csis_irq_handler();
0) 1.375 us | mipi_csis_irq_handler();
------------------------------------------
0) <idle>-0 => gst-lau-892
------------------------------------------
0) 2.250 us | mipi_csis_enable_interrupts.isra.0();
0) 1.875 us | mipi_csis_system_enable.isra.0();
0) * 86738.87 us | } /* mipi_csis_s_stream */
0) * 87064.87 us | } /* v4l2_ioctl */
0) ! 968.875 us | v4l2_ioctl();
0) | v4l2_release() {
0) | mx6s_csi_close() {
0) | mipi_csis_s_power() {
0) | mipi_csis_runtime_suspend() {
0) | mipi_csis_pm_suspend() {
0) 1.500 us | mipi_csis_enable_interrupts.isra.0();
0) 1.750 us | mipi_csis_system_enable.isra.0();
0) 8.250 us | mipi_csis_clk_disable();
0) + 22.375 us | }
0) + 24.625 us | }
0) + 41.125 us | }
0) 1.125 us | mx6s_csi_runtime_suspend();
0) + 63.750 us | }
0) + 74.250 us | }
So I print the error log in mipi_csis_irq_handler:
static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
{
struct csi_state *state = dev_id;
struct csis_pktbuf *pktbuf = &state->pkt_buf;
unsigned long flags;
u32 status;
status = mipi_csis_read(state, MIPI_CSIS_INTSRC);
spin_lock_irqsave(&state->slock, flags);
if ((status & MIPI_CSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) {
u32 offset;
if (status & MIPI_CSIS_INTSRC_EVEN)
offset = MIPI_CSIS_PKTDATA_EVEN;
else
offset = MIPI_CSIS_PKTDATA_ODD;
memcpy(pktbuf->data, state->regs + offset, pktbuf->len);
pktbuf->data = NULL;
rmb();
}
/* Update the event/error counters */
if ((status & MIPI_CSIS_INTSRC_ERRORS) || debug) {
int i;
for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
if (!(status & state->events[i].mask))
continue;
state->events[i].counter++;
printk("%s: %d\n",
state->events[i].name,
state->events[i].counter);
}
printk("status: %08x\n", status);
}
spin_unlock_irqrestore(&state->slock, flags);
mipi_csis_write(state, MIPI_CSIS_INTSRC, status);
return IRQ_HANDLED;
}
-----------------------------------------------------------------------------------------------------------
First, I enable 1280x800, I got the error when I sent "Ctrl + C" to close camera:
root@edm-g-imx8mm:~# gst-launch-1.0 v4l2src device=/dev/video0 ! video/x-raw,width=1280,height=800 ! imxvideoconvert_g2d ! fpsdisplaysink sync=false
Setting pipeline to PAUSED ...
Pipeline is live and does not need PREROLL ...
Pipeline is PREROLLED ...
Setting pipeline to PLAYING ...
New clock: GstSystemClock
^Chandling interrupt.
Interrupt: Stopping pipeline ...
Execution ended after 0:00:03.305730125
Setting pipeline to NULL ...
[ 8936.573147] FIFO Overflow Error: 1
[ 8936.576560] Frame Start: 1
[ 8936.579265] Frame End: 1
[ 8936.581797] status: 01100010
Total showed frames (95), playing for (0:00:03.305677000), fps (28.738).
Then I tried to enable 1280x800 again, I got the error log below that:
root@edm-g-imx8mm:~# gst-launch-1.0 v4l2src device=/dev/video0 ! video/x-raw,width=1280,height=800 ! imxvideoconvert_g2d ! fpsdisplaysink sync=false
Setting pipeline to PAUSED ...
Pipeline is live and does not need PREROLL ...
Pipeline is PREROLLED ...
Setting pipeline to PLAYING ...
New clock: GstSystemClock
[ 71.858138] FIFO Overflow Error: 1
[ 71.861552] Frame Start: 1
[ 71.864258] status: 01000010
[ 71.867166] FIFO Overflow Error: 2
[ 71.870568] status: 00000010
[ 71.875955] FIFO Overflow Error: 3
[ 71.879360] status: 00000010
[ 71.882268] FIFO Overflow Error: 4
[ 71.885673] status: 00000010
[ 71.888569] FIFO Overflow Error: 5
[ 71.891969] status: 00000010
[ 71.909285] FIFO Overflow Error: 6
[ 71.912686] status: 00000010
[ 71.915577] FIFO Overflow Error: 7
[ 71.918975] status: 00000010
[ 71.921865] FIFO Overflow Error: 8
[ 71.925264] status: 00000010
[ 71.942623] FIFO Overflow Error: 9
[ 71.946028] status: 00000010
[ 71.948931] FIFO Overflow Error: 10
...
If I enable 1280x720, it can work and has no error log:
root@edm-g-imx8mm:~# gst-launch-1.0 v4l2src device=/dev/video0 ! video/x-raw,width=1280,height=720 ! imxvideoconvert_g2d ! fpsdisplaysink sync=false
Setting pipeline to PAUSED ...
Pipeline is live and does not need PREROLL ...
Pipeline is PREROLLED ...
Setting pipeline to PLAYING ...
New clock: GstSystemClock
0:00:04.9 / 99:99:99.