Cache line size for A7 in i.MX7D

[ko-hey]

Hi all

Could someone tell me the cache line size for A7 in i.MX7D ?

I read a reference manual and found only for M4.

Please tell me the size of cache line for A7 of i.MX7D.

Ko-hey

[Yuri · Accepted solution]

Hello

  from the  ARM Information Center :

 * instruction side cache line length of 32-bytes ;

 * data side cache line length of 64-bytes.

Have a great day,
Yuri

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[ko-hey]

Hello 

Thank you for support.

I found it in technical reference manual too.

Cortex-A7 MPCore Revision: r0p3 Technical Reference Manual 

L1: instruction side cache line length of 32-bytes

      data side cache line length of 64-bytes

L2: fixed line length of 64 bytes

Ko-hey