CLKO Terminology, Meaning of CLK_OUT_ SEL

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CLKO Terminology, Meaning of CLK_OUT_ SEL

Contributor III

Hi All

I am confused by the terminology used in the i.MX6Q manual to describe how exactly the CLKO1 and CLKO2 signals are switched.

I understand that there are two big muxes that select, which clock should appear on the CLK1 and CLK2 output. But there seems to be another Mux that is configured by the CLK_OUT_ SEL bit in the CCM_CCOSR register.

The exact description in the manual (Rev. 2, 06/2014) is:

8 CLK_OUT_SELCCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks
0 CCM_CLKO1 output drives CCM_CLKO1 clock
1 CCM_CLKO1 output drives CCM_CLKO2 clock


  • Is the output of this Mux connected to the CLK1 or CLK2 pad?
  • Is it connected before or after either of the dividers?

A little diagram would be wonderful. If you explain this to me in detail (preferrably with names attached to each signal) I'll draw a diagram and post it here ;-)

I need to know the details because I have to configure a clock to appear on CLK1 from the linux device tree, so I have to reflect the topology there.

Best Regards

Florian Dörfler

PS: I'm not the only one who finds this unclear. My american colleague (an FPGA designer) could not tell me either what is meant in the manual.

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NXP TechSupport
NXP TechSupport

Hi Florian

CLK_OUT_ SEL bit selects which clock will be outputted when enabled CLKO_EN:

for example when CLK_OUT_SEL=1, CCM CLKO1_DIV settings outputs on CCM_CLKO2

CCM_CLKO1, CCM_CLKO2 are given in Table 4-1. Pin Assignments i.MX6Q RM

Best regards
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