CCM register setting value of i.MX6Dual.

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CCM register setting value of i.MX6Dual.

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Contributor III

Dear community.

Our customer has question below.

Please tell me the function explanation and default set value of register of CCM described in IMX6DQRM.

CCM_ANALOG_PLL_ARMn

bit17LVDS_SEL      

bit18LVDS_24MHZ_SEL  

bit19PLL_SEL          

CCM_ANALOG_PLL_SYSn

bit18PFD_OFFSET_EN

CCM_ANALOG_PLL_AUDIOn

bit18PFD_OFFSET_EN

CCM_ANALOG_PLL_VIDEOn

bit18PFD_OFFSET_EN

CCM_ANALOG_PLL_ENETn

bit18PFD_OFFSET_EN

bit19ENABLE_125M

bit20ENABLE_100M

Thank you,

Best Regards.

Takashi.

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NXP TechSupport
NXP TechSupport

Hello Takashi Takahashi,

I received confirmation that in general these are debug or reserved bits that do not need to be programmed by the customer.

CCM_ANALOG_PLL_ARMn

bit17LVDS_SEL      

bit18LVDS_24MHZ_SEL  

bit19PLL_SEL      

In this case the default value is the one shown on the Reference Manual.

  pastedImage_4.png

 

CCM_ANALOG_PLL_SYSn

CCM_ANALOG_PLL_AUDIOn

CCM_ANALOG_PLL_VIDEOn

CCM_ANALOG_PLL_ENETn

bit18PFD_OFFSET_EN

 As for PDF_OFFSET_EN, this is a test bit. PDF stands for Phase Frequency Detector, not Phase Fractional Divider. The purpose of it is to reduce PLL charge pump nonlinearity. It should not be programed and it will be updated on future releases as reserved.

 

CCM_ANALOG_PLL_ENETn

bit19ENABLE_125M

bit20ENABLE_100M

The ENABLE_100M and ENABLE_125M bits in CCM_ANALOG_PLL_ENET enable the output of 100MHz clock and 125MHz clock from the ENET PLL, respectively. 100M clock is used for SATA and the 125M clock is used for PCIe.

I hope this information clarifies your concerns!

Regards,

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NXP TechSupport
NXP TechSupport

Hello Takashi Takahashi,

I’m looking for more details on these registers. I’ll update this thread as soon as I have more information.

Regards,

 

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NXP TechSupport
NXP TechSupport

Hello Takashi Takahashi,

I received confirmation that in general these are debug or reserved bits that do not need to be programmed by the customer.

CCM_ANALOG_PLL_ARMn

bit17LVDS_SEL      

bit18LVDS_24MHZ_SEL  

bit19PLL_SEL      

In this case the default value is the one shown on the Reference Manual.

  pastedImage_4.png

 

CCM_ANALOG_PLL_SYSn

CCM_ANALOG_PLL_AUDIOn

CCM_ANALOG_PLL_VIDEOn

CCM_ANALOG_PLL_ENETn

bit18PFD_OFFSET_EN

 As for PDF_OFFSET_EN, this is a test bit. PDF stands for Phase Frequency Detector, not Phase Fractional Divider. The purpose of it is to reduce PLL charge pump nonlinearity. It should not be programed and it will be updated on future releases as reserved.

 

CCM_ANALOG_PLL_ENETn

bit19ENABLE_125M

bit20ENABLE_100M

The ENABLE_100M and ENABLE_125M bits in CCM_ANALOG_PLL_ENET enable the output of 100MHz clock and 125MHz clock from the ENET PLL, respectively. 100M clock is used for SATA and the 125M clock is used for PCIe.

I hope this information clarifies your concerns!

Regards,

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