CCM_CLKO1 set to 24.576 MHz

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CCM_CLKO1 set to 24.576 MHz

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johnturnur
Contributor III

Hi,

How can i set CCM_CLKO1 to 24.576 MHz?

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AnsonHuang
NXP Employee
NXP Employee

Hi, John

     Are you using i.MX6 series SOC? If yes, then I think you can just set the CCM_CLKO1 to output a clock source which listed in the CCM_CCOSR, both clko1_sel and clko2_sel can be set to output to CCM_CLKO1. But I am not sure whether there is a clock source in the list having its freq=24.576MHz. if yes, then you can get it, just need to set the IOMUX to CCM_CLKO, then set the CCM_CCOSR register to select the clock source you wanted.

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xiongweihuang
Contributor III

Hello all

I use imx6 Solo

with 24M crystal as source .

I tried from osc_clock and pll4 clock

In my test , CCM_CLKO1 just output 24M not 24.576M,even from pll4 , I set pll4 with (24*(12+288/1000))/4

And , with CLKO2_EN , CLK02_DIV = 7 ,CLKO2_SEL = 2 CLK_OUT_SET = 1  from usdhc4 usdhc4 use 198M clock ,I just get 49.5M not 24.75M

Do you have any errta about this ?

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AnsonHuang
NXP Employee
NXP Employee

Hi, John

     Are you using i.MX6 series SOC? If yes, then I think you can just set the CCM_CLKO1 to output a clock source which listed in the CCM_CCOSR, both clko1_sel and clko2_sel can be set to output to CCM_CLKO1. But I am not sure whether there is a clock source in the list having its freq=24.576MHz. if yes, then you can get it, just need to set the IOMUX to CCM_CLKO, then set the CCM_CCOSR register to select the clock source you wanted.

View solution in original post

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fangmingan
Contributor I

Dear Yongcai,

When cpu imx6  is in sleep status, CCM_CLKO1 still can provide clock?

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AnsonHuang
NXP Employee
NXP Employee

What do you mean by sleep? SOC in WAIT mode or STOP mode?

CKO can output clock as long as its source clock is there.

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058

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fangmingan
Contributor I
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fangmingan
Contributor I

Thanks your response!

select CCM_CLKO1 to 32.768Hhz  by setting CLKO1_SEL 1110 ckil_sync_clk_root. then soc enter wait or standby mode.

I can't find whether ckil_sync_clk_root is available  on wait or standby mode on <IMX6DQRM.pdf>

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