CCM_CLKO1 on GPIO1_IO05 pad

[sebastianbartko]

Hi All,

I wonder if there is any additional step needed to set GPIO1_IO5 pad to CCM_CLKO1 output

I can easly set it for GPIO1_IO0 as this is its default location, but also i can set it simultanously on CSI0_HSYNC pad (ALT3), but not on GPIO1_IO05.

I've verified both settings for CCM module registers and IOMUX registers, but still no joy

I've also verified that i acually have control over GPIO1_IO5 pad setting it into GPIO mode and driving it manually, also i've tested my settings on another hardware to exclude any hardware malfunction - as i said, with no luck.

Anyways, if someone could point me in right direction i would apreciate it. for this point i'm assuming this is imx6 core bug

Please advise

Best regards,

Sebastian

[sebastianbartko]

Hi Igor,

I wrote a little utility to read and write any hardware registers SoC has, and i'm confident there is no redundant setting in that pad - it reads 0x00000003 exacly as it suppose to do.

Best regards,

 Sebastian

[igorpadykov]

Hi Sebastian

could you check attaching jtag immediately after chip reset and set iomux

settings with it.

Best regards
igor

[sebastianbartko]

Hi Igor,

exact part number is MCIMX6Q6AVT08AD,

I'm confident that no part of software is touching this pin before i make my changes, as i'm able to modify these registers after system is fully booted up.

if this has any inpact, previosuly this pin was used as part of i2c3 interface, but i've removed any reference to it and zeroed apropriate daisy chaining registers.

Best regards,

 Sebastian

[igorpadykov]

Hi Sebastian

one can printf iomux settings of GPIO1_IO5 pad to check if

it was left in i2c configuration for some reason.

Best regards
igor

[igorpadykov]

Hi Sebastian

what processor (full name) used in the case ?

Is GPIO1_IO05 listed as allowable option for CCM_CLKO1

in IOMUX Chapter of Reference Manual. Could it be used

already in uboot/linux as part of other interface.

Best regards
igor
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