CCM_CLKO1 12.888MHz +/-2949Hz.

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CCM_CLKO1 12.888MHz +/-2949Hz.

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jorgecorado
Contributor II

Hi All,

We need to create a delay on the I2S master clock (CCM_CLKO1). The frequency has to be 12.888MHz +/-2949Hz.

I have two questions:

-     Can we have this range of frequencies (12.888MHz +/-2949Hz.) in CCM_CLKO1?

-     Can we move between this range of frequencies with no interruption of I2S communication?

My Quad i.MX6 P/N is MCIMX6Q6AVT10AC.

My kernel version is 3.14

Thanks for your help

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jorge

CCM_CCOSR has dividers for CLKO output.

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sheldonlrucker
Contributor IV

Hello Igor,

I work with Jorge and have been helping with trying to set PLL4's output frequency.

We've tried the following register settings.

# CCM_CCOSR

# enable clk0 output, divide by 8, pll4 out

memtool 20C4060=10E00FF

# CCM_ANALOG_PLL clear DIV_SELECT

memtool 20C8078=7F

# CCM_ANALOG_PLL set DIV_SELECT to 27

memtool 20C8074=0000202B

Above sets CLKO1_DIV to 8 which is the maximum divider for clock 01 output.   We then set PLL4's div to the lowest suggested range of 27.  This results in a PLL4 frequency of 32.42 MHz which is above our desired 12.288 MHz. 

If we leave CCM_ANALOG_PLL's DIV_SELECT to its default value of 6 then we can get a lower frequency for PLL4 of 16.6MHz but this  DIV_SELECT value is lower than the allowable range per the "Valid range for DIV_SELECT divider value: 27~54" note in the reference manual.

In all of the above cases CCM_ANALOG_PLL_AUDIO_NUM was set to 05F5E100 and CCM_ANALOG_PLL_AUDIO_DENOM was set to 2964619C.

So in all of the above tests we've been unable to reach a frequency of 12.288 MHz.  Is this possible?  If so would you please guide us as to which bits we need to set in which registers?  We've tried all of your previous suggestions without luck.

Thank you,

Sheldon

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Sheldon

could you try to change CCM_ANALOG_MISC2n, field

AUDIO_DIV_MSB,AUDIO_DIV_LSB

Best regards

igor

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sheldonlrucker
Contributor IV

I tried setting both the MSB and LSB audio div to 4x in the CCM_ANALOG_MISC2n register and it didn't seem to change the frequency of PLL4.  Is there something I need to do after setting the MSB and/or LSB so that the changes will take effect?

Thank you,

Sheldon

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igorpadykov
NXP TechSupport
NXP TechSupport

there is another option of ssin_clk_root in CCM_CCOSR, this should correspond

SSI's sys clock in Table 61-7. SSI Bit Clock and Frame Rate as a Function of PSR,

PM, and DIV2  i.MX6DQ Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Regarding CCM_ANALOG_MISC2n[MSB:LSB] this divider does not exist,

sorry for confusion.

Best regards

igor

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jorge

yes, right

 

Best regards

igor

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jorgecorado
Contributor II

Hi Igor,

Since the lower value for DIV_SELECT is 27, we need a really low source frequency (FREQ) to reach the final 12.288MHz output., something around 0.47265 MHz. Thus, the formula goes like this:

PLL Output Frequency = FREQ*(DIV_SELECT+(NUM/DENOM))   -------->    12.2889 = (0.47265*(27+(-999999999/1000000000))

How can we get that small frequency (FREQ)?

Do we have to take the Source 24MHz and divided several times to get something close to 0.47265MHz? If so, can you give us a better idea how to do this?

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jorge

> Can we have this range of frequencies (12.888MHz +/-2949Hz.) in CCM_CLKO1?

yes, by appropriatley reprogramming PLLs which feed that clock, please check CCM chapter of RM

> Can we move between this range of frequencies with no interruption of I2S communication?

I am afraid suh case was not tested before, one  can try but result is not guaranteed.

Best regards

igor

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jorgecorado
Contributor II

Hi Igor,

Thanks for your prompt answer.

Could you please give us some directions about which CMM registers we have to play with, in order to have that frequency.

Thanks

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jorge

please read CCM chapter of RM, register descriptions of

CCM_CCOSR, CCM_ANALOG_PLL_XX, check figures of

clocks generation. Then reprogram suitable CCM_ANALOG_PLL_XX

PLL and route clock from it using CCM_CCOSR.

Best regards

igor

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jorgecorado
Contributor II

Hi Igor,

I have a questions about the following formula to calculate the PLL output frequency:

PLL Output Frequency = FREQ*(DIV_SELECT+(NUM/DENOM))

The Datasheet indicate: "Valid range for DIV_SELECT divider value: 27~54."

Is this the range (27 -54) that we have to use for the formula mentioned above?

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csoapy
Contributor III

It's not a FREQ, but Fref == FREQref

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