Ok, i think the problem is that
/sys/class/tty/ttymxc0/uartclk = 24000000 Hz
on mainline kernel. maximal achievable baudrate is uartclk/16, which is 1.5M in this case of 24MHz
any idea how to reconfigure this uart to use some faster clock on upstream kernel (eg. 48M), so i can achieve 3M baudrate?
Currently in device tree the uart1 has following configuration:
clocks = <&clk IMX8MM_CLK_UART1_ROOT>, <&clk IMX8MM_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
Is it possible to change it to use some faster clock? I've read that people use 80MHz instead of 24MHz.
Update: it helped to add following:
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
but currently i have DMA disabled and geting occasional data corruption, not sure if that will work correctly. have to try with DMA again, but that caused issues previously.
Update 2: with SDMA enabled it does freeze when trying to access the UART.
