BusFreq IMX driver in mainline kernel?

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

BusFreq IMX driver in mainline kernel?

3,191件の閲覧回数
Harvie
Contributor II

Hello

are there any chances of getting busfreq driver running on mainline kernel?

it seems to me that i am not able to reliably run UART at speeds higher than 1M baud without it... (i am looking for 3M baud serial communication)

ラベル(2)
タグ(1)
0 件の賞賛
返信
7 返答(返信)

3,157件の閲覧回数
joanxie
NXP TechSupport
NXP TechSupport

pls refer to the chapter  2.5.4 Dynamic Bus Frequency of enclosed file

0 件の賞賛
返信

3,152件の閲覧回数
Harvie
Contributor II

Thank you. I've read everything in that chapter, unfortunately that does not explain my issues with serial communication using mainline kernel...

0 件の賞賛
返信

3,128件の閲覧回数
joanxie
NXP TechSupport
NXP TechSupport

what processors do you use? did you have this issue on nxp bsp? what's your mainline version?

0 件の賞賛
返信

3,096件の閲覧回数
Harvie
Contributor II

Hello,

IC package says MIMX8MM6CV1KZAA,

i've tried several mainline versions. Mostly 5.15.18,

with BSP kernel i do not have this issue.

 

 

0 件の賞賛
返信

3,071件の閲覧回数
joanxie
NXP TechSupport
NXP TechSupport

since you test nxp bsp successfully, I couldn't reproduce this issue on my side, could you share more detailed information about your issue, let me check if we have patch or anything else useful information for you, but we don't maintain mainline kernel

0 件の賞賛
返信

2,900件の閲覧回数
Harvie
Contributor II

Ok, i think the problem is that

/sys/class/tty/ttymxc0/uartclk = 24000000 Hz

on mainline kernel. maximal achievable baudrate is uartclk/16, which is 1.5M in this case of 24MHz

any idea how to reconfigure this uart to use some faster clock on upstream kernel (eg. 48M), so i can achieve 3M baudrate?

 

Currently in device tree the uart1 has following configuration:

clocks = <&clk IMX8MM_CLK_UART1_ROOT>, <&clk IMX8MM_CLK_UART1_ROOT>;
clock-names = "ipg", "per";

Is it possible to change it to use some faster clock? I've read that people use 80MHz instead of 24MHz.

 

Update: it helped to add following:

assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;

 but currently i have DMA disabled and geting occasional data corruption, not sure if that will work correctly. have to try with DMA again, but that caused issues previously.

 

Update 2: with SDMA enabled it does freeze when trying to access the UART.

0 件の賞賛
返信

2,906件の閲覧回数
Harvie
Contributor II

Do you have patch to get UART working reliably on 3M baudrate with upstream kernel?

(5.15.18 or newer)

0 件の賞賛
返信