Boundary scan test of DDR3 SDRAM connected to IMX6

[DasBert33]

Hello all,

I have to develop a JTAG test for a board hosting an IMX6, using a XJTAG tester.

My JTAG testing works fine for most IOs, and only DDR3 testing works very unreliably and inconsistent over boards. Of the 4 memory ICs tested 2 often fail. In regular non-JTAG mode the SDRAM works just ok.

I strongly suspect a signal integrity issue, where the IOs on the IMX are not using correct driverstrength/termination settings in JTAG mode, causing my SDRAM test to fail often.

Is there a way to influence drivestrength settings over the JTAG interface? How can I make sure that correct IO drive settings are used in JTAG mode?

I assume I can set the required settings over JTAG using the 'ENABLE_ExtraDebug' instruction, but it is unclear how. Can you please provide a register map/list of the registers that can be set using this instruction?

Thanks in advance,

Bert

[DasBert33]

Hello,

I just discovered that an older device, IMX53, seems to contain the information I am looking for. Looing in iMX53RM.pdf, p436, a larger memory map can be found documenting the registers I am looking for, in a chapter called 'System Debug SJC Memory Map/Register Definition'. And more specifically I am interested in register 0xB, SJC_GPUCR3 of the register map, as it contains various drive and SDRAM related settings.

Does someone have the same register map information for iMX6? It would be nice to see where the SJC_GPUCR3 register is different on iMX6 compared to iMX53.

Bert

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

I could see this very similar issue.

Maybe it can help you to debug that you are performing the initialization correctly and use the appnote linked to confirm the sequences.

Regards

[DasBert33]

Hello Joseph,

Thanks for the swift reply. However I am not sure whether the proposed topics are applicable to my usecase of JTAG/boundary scan testing.

I am creating a test for a PCB/board hosting an iMX6, using boundary scan only. I am not accessing any internal resources (registers) such as the memory controller. Instead I am only toggling IO pins by scanning in/out vectors over the JTAG interface. This works fine for all IO connections I need to test, except for the SDRAM IOs. The SDRAM test does work occassionally but also fails often, which leads me to think there is an issue with the default IO settings of the SDRAM pins in boundary scan JTAG mode. 

Can I influence the IO settings (drive strength, termination, ...) when using the device in JTAG boundary scan mode only?

I suspect I can use the 'ENABLE_ExtraDebug' JTAG instruction to set applicable register(s) correctly, but the reference manual only documents 8 registers (addr 0 to 7) that are not applicable to the IOs. I do think I need this 'ENABLE_ExtraDebug' instruction because I received a JTAG command from XJTAG that fixes an erratum boundary scan issue (ERR009218) I was also having. It fixes it by setting a better drivestrength value to EIM pins. This is a write to a (undocumented in the RM) register at addr 11.

It would be nice to get the documentation on all JTAG 'Enable_ExtraDebug' registers that influence IOs, and especially SDRAM pin related registers.

BR,

Bert

[JosephAtNXP]

Hi @DasBert33,

Seems like other customers have had this issue when testing EIM interface and DDR in other i.MX series products, it's likely a pin initialization of DDR failed and the workaround is indeed an ENABLE_EXTRADEBUG instruction. This are the registers for DRAM pins configuring.

DDR_PHY_DRVDS_CON0 (0x3079009C) for the Command, Address, clock pads

DDR_PHY_ZQ_CON0 (0x307900C0) for the DQS, DQ, DM pads

And an advise to use the ENABLE_EXTRADEBUG correctly is to:

Make sure that the 38bit configuration value gets applied to the upper 38 bits of the 70 bit register accessed by the 5'b00100 instruction code, then you can configure these troublesome I/Os to be able to drive.

Regards,

[DasBert33]

Hello Joseph,

Thank you for confirming I need an extra JTAG instruction for the SDRAM interface to work properly.

However the mentioned registers do not make sense for my i.MX6, I cannot find any reference of these exact registers in the reference manual (iMX6DQPRM.pdf). Can you please share where you got the other registers from?

I do find regular registers in the RM that seem related to my needs (IOMUXC_SW_PAD_CTL_PAD_DRAM_*) but I don't know how to set them over the JTAG interface using the Enable_Extradebug instruction. 

According to the RM I am using the Enable_Extradebug instruction contains 38bits: 1r/w bit, 5 address bits and 32bits datafield. That seems to suggest I can set up to 32 different registers (2**5) with data of which 8 are documented in the manual. That seems not to match to your earlier suggestion. Can you elaborate on how should I set the SDRAM IO settings using this interface/instruction?

BR,

Bert