Hi community,
I have a question about i.MX6 DDR Stress Test in https://community.freescale.com/docs/DOC-96412.
Please see the attached file.
I understand the stress test tool output a center of delay setting values which can work DDR correctly as attached file (Case A, B).
Then, how about Case C?
The stress test tool can output a suitable setting? or it judge it is NG?
Best Regards,
Satoshi Shimoda
Solved! Go to Solution.
Hi Shimoda,
The valid range of DG_HC_DEL is to 0b1101 and DG_DL_ABS_OFFSET is to 0b1111111,
and the total read DQS gating delay is (DG_HC_DEL#)*0.5*cycle + (DG_DL_ABS_OFFSET#)*1/256*cycle.
The suitable delay range can't be out of valid DQS gating delay range.
Grace
Hi Shimoda,
The valid range of DG_HC_DEL is to 0b1101 and DG_DL_ABS_OFFSET is to 0b1111111,
and the total read DQS gating delay is (DG_HC_DEL#)*0.5*cycle + (DG_DL_ABS_OFFSET#)*1/256*cycle.
The suitable delay range can't be out of valid DQS gating delay range.
Grace