I found following description in datasheet. It means that iMX8QXP will output high signal after watchdog timer is expired.
Is it right? Can I assert SCU_WDOG_OUT signal any other way?
"And if hardware had connected the SCU_WDOG_OUT pin from iMX8QXP to PMIC's WDI pin, then during SOC reset, the PMIC will also do hard reset to make a POR reboot for the whole system.”
We also have to configure IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT isn't it? If so, which node should use this ball configuration? For example, imx8mp has a wdog1 node for this purpose, is there any equivalent for QXP as well?
1)It means that iMX8QXP will output high signal after watchdog timer is expired.
> do you mean after watchdog timer is reset?
2)pls find the pic as below about reset case
I appreciate your support.
Currently we are connecting SCU_WDOG_OUT pin to PMIC's WDI pin same as MEK design.
When iMX assert SCU_WDOG_OUT, PMIC will start the reset operation.
therefore, I would like to know the conditions under which SCU_WDOG_OUT is asserted.
iMX8DX contain two watchdog modules in SCU and M4 subsytem.
I don't understand the relevance of both modules to SCU_WDOG_OUT pin.
refer to the Reference Manual, After loading an image. If the image is bigger than the size which can be loaded
within the WDOG timeout, depending on the image size and the speed of the boot interface, a WDOG timeout will occur and the chip will reset.
for M4 and SCU, This chip features one configurable Cortex-M4 subsystem and a dedicated Cortex-M4 subsystem within the SCU,The SCU is made of a Cortex-M4 processor and a set of peripherals and interfaces to connect to external PMIC and to control internal subsystems.
one also can refer to the SCFW document as below, pls focus on the