By the way, did you measure the pixel clock output from iMX6?
When you change adv739x from IPU1 to IPU2, the clock.c should also be modified
From
clk_set_parent(&ipu1_di_clk[0], &pll3_pfd_540M); //for CVBS 27MHz clock
clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
To
clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
clk_set_parent(&ipu2_di_clk[0], &pll3_pfd_540M); //for CVBS 27MHz clock
clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);