BT1120 1080p capture on imx6q ipu1-CSI1 in linux4.1

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BT1120 1080p capture on imx6q ipu1-CSI1 in linux4.1

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Contributor II

Hi,

 

I'm using an i.mx6q sabrelite with a kernel  4.1.15

There is a BT1120 1080P  SDR video form FPGA  connected on IPU1-CSI1 (parallel mode),

the video souce of FPGA is gs2971. The connect as follows  GS2971<------>FPGA<----->imx6q .

 FPGA  configure GS2971 output BT1120 1080P  SDR 16bit ,and the frequence of pclk is 74.25MHz. 

the pin mapping between imx6q and FPGA  is CSIx_DAT2 ~ CSIx_DAT9 <----> C[0] ~ C[7], CSIx_DAT12 ~ CSIx_DAT19 <----> Y[0] ~ Y[7].  according to "《IMX6DQCEC.PDF》 table 66  YCBCR7 16BIT "  and The SAV and EAV  are embedded. 

the HS, VS,DATAEN, PCLK has been connected to imx6q.

i created a driver, and communicate to V4l2 driver ,and the following steps has been done.

1、arch/arm/mach-imx/mach-imx6q.c

to enbale IPU1-CSI1 and IPU0-CSI0

regmap_update_bits(gpr, IOMUXC_GPR1, 3 << 19, 3 << 19);  

2、 arch/arm/boot/dts/imx6qdl-sabresd.dtsi 

set pinmux:

pinctrl_ipu2_2: ipu2grp-2 { /* ipu2 parallel camera */
fsl,pins = <
MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x10000
MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x10000
MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0xb0b1
MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0xb0b1
MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0xb0b1
MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0xb0b1
MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0xb0b1
MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0xb0b1
MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0xb0b1
MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0xb0b1
MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x10000
MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10000
MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1
MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1
MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1
MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1
MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1
MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1
MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1
MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0xb0b1
MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1
MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x10000
MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x10000
MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1
>;
};

set driver :

gs2971: gs2971@5c {
compatible = "gs2971";
reg = <0x5c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu2_2>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "csi_mclk";
csi_id = <1>;
mclk = <77856768>;
mclk_source = <0>;
cvbs = <1>;
};

v4l2_cap_1 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <1>;
csi_id = <1>;
mclk_source = <0>;
status = "ok";
};

3、add the slave driver 

add file  "drivers/media/platform/mxc/capture/gs2971.c" and modify kconfig and Makefile

4、modify ipu driver for Support BT1120 progressive mode

drivers/mxc/ipu3/ipu_capture.c

drivers/media/platform/mxc/capture/v4l2-int-device.h

drivers/media/platform/mxc/capture/mxc_v4l2_capture.c

 has been changed .

5、use mxc_v4l2_capture.out to test

./mxc_v4l2_capture.out -iw 1920 -ih 1080 -ow 1920 -oh 1080 -d /dev/video1 -r 1 -c 2  -f YUYV -fr 30 frame.yuv

out_width = 1920, out_height = 1080
top = 0, left = 0
sensor chip is gs2971_decoder
sensor supported frame size:
720x576
Width = 1920 Height = 1080 Image size = 4147200
pixelformat: YUYV
imx-ipuv3 2800000.ipu: IC output size(1080) cannot exceed 1024
imx-ipuv3 2800000.ipu: failed to calculate prpenc height scaling coefficients
ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0
VIDIOC_DQBUF failed.
buf.index 0
ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0
VIDIOC_DQBUF failed.
buf.index 0

/dev/video0  for IPU0-CSI0  (PAL video  720x576 )  and video0 can capture image

dump ipu1-csi1 some register

CSI_SENS_CONF 0xa50

CSI_SENS_FRM_SIZE 0x437077f

CSI_ACT_FRM_SIZE 0x437077f

CSI_OUT_FRM_CTRL 0x0

what else can I do for this issue?  Any help appreciated

 

reference from:

BT1120 1080P connect to imx6q 

Support BT1120 progressive mode in Mx6Q 

Patch to support adv7180 TVin chip for Freescale Android R10.4 BSP on iMX53 -blog archive 

BT.1120 capture on i.mx6q CSI1 using linux 

https://community.nxp.com/thread/311765#348083 

i.MX6 CSI-interface and .BT1120 

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NXP Employee
NXP Employee

I think you can apply the "0001-IPU-update-IPU-capture-driver-to-support-up-to-four-.patch" patch from https://community.nxp.com/docs/DOC-328548. Of cource, you need pay attention to the GPR1 register setting.

As I remembered, the default BSP has some issue on IPU2 CSI1 camera capture.

And you'd better to use the mxc_v4l2_tvin test application to capture the camera, the mxc_v4l2_capture will not capture the original video, it will ge through IC, then the output width and height must be less than 1024.

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Contributor II

hi qiang 

linux 4.1.5 can use this "0001-IPU-update-IPU-capture-driver-to-support-up-to-four-.patch" patch? Many patchs are not suitable for the 4.1.5 kernel .

 “the default BSP has some issue on IPU2 CSI1 camera capture.”  tit's that not configured properly in default BSP ?

my IPU2 CSI1 configuration step 1 and step 2  is correct In my question?

the IOMUXC_GPR1 reg val

IOMUXC_GPR1 reg = 0x487C1005 

i'll try to use mxc_v4l2_tvin test .

regards

 

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NXP TechSupport
NXP TechSupport

refer to your error message, it seems you use IC moudle, which has limitation on output (1024x1024), and it seems you use default IC in the mxc_v4l2_output.out, you can try to use option "-i 1" for CSI->MEM path directly, not use IC

28 Views
Contributor II

I use these commands,but it still not work:

./mxc_v4l2_capture.out -iw 1920 -ih 1080 -ow 1920 -oh 1080 -d /dev/video1 -i 1 -r 1 -c 1  -f YUYV -fr 30 frame.yuv

in_width = 1920, in_height = 1080
out_width = 1920, out_height = 1080
top = 0, left = 0
sensor chip is gs2971_decoder
sensor supported frame size:
720x576
Width = 720 Height = 624 Image size = 898560
pixelformat: YUYV
VIDIOC_DQBUF failed.
buf.index 0

./mxc_v4l2_tvin.out -d 1 -ow 1920 -oh 1080 -f YUYV
TV decoder chip is gs2971_decoder
driver=mxc_vout, card=DISP3 FG, bus=, version=0x0004010f, capabilities=0x84200002
fmt RGB565: fourcc = 0x50424752
fmt BGR24: fourcc = 0x33524742
fmt RGB24: fourcc = 0x33424752
fmt RGB32: fourcc = 0x34424752
fmt BGR32: fourcc = 0x34524742
fmt NV12: fourcc = 0x3231564e
fmt UYVY: fourcc = 0x59565955
fmt YUYV: fourcc = 0x56595559
fmt YUV422 planar: fourcc = 0x50323234
fmt YUV444: fourcc = 0x34343459
fmt YUV420: fourcc = 0x32315559
fmt YVU420: fourcc = 0x32315659
fmt TILED NV12P: fourcc = 0x50564e54
fmt TILED NV12F: fourcc = 0x46564e54
fmt YUV444 planar: fourcc = 0x50343434
start time = 1527239359 s, 337933 us
VIDIOC_DQBUF failed.

the cis1 reg  as follows

[ 221.509909] hyy_debug: CSI_SENS_CONF 0x8a53
[ 221.509918] hyy_debug: CSI_SENS_FRM_SIZE 0x437077f
[ 221.509923] hyy_debug: CSI_ACT_FRM_SIZE 0x437077f
[ 221.509927] hyy_debug: CSI_OUT_FRM_CTRL 0x0
[ 221.509932] hyy_debug: CSI_TST_CTRL 0x0
[ 221.509936] hyy_debug: CSI_CCIR_CODE_1 0x1040030
[ 221.509941] hyy_debug: CSI_CCIR_CODE_2 0x0
[ 221.509945] hyy_debug: CSI_CCIR_CODE_3 0xff0000

so What's wrong with my configuration?

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NXP Employee
NXP Employee

You can check this document: https://community.nxp.com/docs/DOC-332679

By the way, since your pixel clock frequency is high, you also need pay attention to hardware signal quality, maybe you can adjust your input source to reduce the frequency and try.

28 Views
Contributor II

thank you very much,This is very useful。

according to this document: https://community.nxp.com/docs/DOC-332679

the CSI Configuration that I have configured

CSI_EXT_VSYNC = 0x0, internal VSYNC mode.
CSI_DATA_WIDTH = 0x1, 8 bits per color. 
CSI_SENS_DATA_FORMAT = 0x1, YUYV format. 
CSI_SENS_PRTCL = 0x5, BT.1120 SDR progressive mode
IPU_CSI_SENS_FRM_SIZE 
For 1080p, 1920x1125   value=0x464077f
IPU_CSI_ACT_FRM_SIZE
For 1080p, 1920x1080   value=0x473077f
IPU_CSI_OUT_FRM_CTRL
0x0;
IPU_CSI_CCIR_CODE_1
0x40010 
IPU_CSI_CCIR_CODE_2
0x0
IPU_CSI_CCIR_CODE_3
0xFF0000 

according to bt.1120 protocol  FPGA set the video as follows

1080p  1 Frame = 41 lines vertical blanking + 1080 line active video + 4 lines vertical blanking

SAV  
FF 00 00 B6  in blanking 
FF 00 00 9d  in active
SAV
FF 00 00 AB  in blanking 
FF 00 00 80   in active

but it still not work

Is there any problem with software configuration or FPGA vdeio source? 

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