I think you can apply the "0001-IPU-update-IPU-capture-driver-to-support-up-to-four-.patch" patch from https://community.nxp.com/docs/DOC-328548. Of cource, you need pay attention to the GPR1 register setting.
As I remembered, the default BSP has some issue on IPU2 CSI1 camera capture.
And you'd better to use the mxc_v4l2_tvin test application to capture the camera, the mxc_v4l2_capture will not capture the original video, it will ge through IC, then the output width and height must be less than 1024.
linux 4.1.5 can use this "0001-IPU-update-IPU-capture-driver-to-support-up-to-four-.patch" patch? Many patchs are not suitable for the 4.1.5 kernel .
“the default BSP has some issue on IPU2 CSI1 camera capture.” tit's that not configured properly in default BSP ?
my IPU2 CSI1 configuration step 1 and step 2 is correct In my question?
the IOMUXC_GPR1 reg val
IOMUXC_GPR1 reg = 0x487C1005
i'll try to use mxc_v4l2_tvin test .
refer to your error message, it seems you use IC moudle, which has limitation on output (1024x1024), and it seems you use default IC in the mxc_v4l2_output.out, you can try to use option "-i 1" for CSI->MEM path directly, not use IC
I use these commands，but it still not work：
./mxc_v4l2_capture.out -iw 1920 -ih 1080 -ow 1920 -oh 1080 -d /dev/video1 -i 1 -r 1 -c 1 -f YUYV -fr 30 frame.yuv
in_width = 1920, in_height = 1080
out_width = 1920, out_height = 1080
top = 0, left = 0
sensor chip is gs2971_decoder
sensor supported frame size:
Width = 720 Height = 624 Image size = 898560
./mxc_v4l2_tvin.out -d 1 -ow 1920 -oh 1080 -f YUYV
TV decoder chip is gs2971_decoder
driver=mxc_vout, card=DISP3 FG, bus=, version=0x0004010f, capabilities=0x84200002
fmt RGB565: fourcc = 0x50424752
fmt BGR24: fourcc = 0x33524742
fmt RGB24: fourcc = 0x33424752
fmt RGB32: fourcc = 0x34424752
fmt BGR32: fourcc = 0x34524742
fmt NV12: fourcc = 0x3231564e
fmt UYVY: fourcc = 0x59565955
fmt YUYV: fourcc = 0x56595559
fmt YUV422 planar: fourcc = 0x50323234
fmt YUV444: fourcc = 0x34343459
fmt YUV420: fourcc = 0x32315559
fmt YVU420: fourcc = 0x32315659
fmt TILED NV12P: fourcc = 0x50564e54
fmt TILED NV12F: fourcc = 0x46564e54
fmt YUV444 planar: fourcc = 0x50343434
start time = 1527239359 s, 337933 us
the cis1 reg as follows
[ 221.509909] hyy_debug: CSI_SENS_CONF 0x8a53
[ 221.509918] hyy_debug: CSI_SENS_FRM_SIZE 0x437077f
[ 221.509923] hyy_debug: CSI_ACT_FRM_SIZE 0x437077f
[ 221.509927] hyy_debug: CSI_OUT_FRM_CTRL 0x0
[ 221.509932] hyy_debug: CSI_TST_CTRL 0x0
[ 221.509936] hyy_debug: CSI_CCIR_CODE_1 0x1040030
[ 221.509941] hyy_debug: CSI_CCIR_CODE_2 0x0
[ 221.509945] hyy_debug: CSI_CCIR_CODE_3 0xff0000
so What's wrong with my configuration？
You can check this document: https://community.nxp.com/docs/DOC-332679
By the way, since your pixel clock frequency is high, you also need pay attention to hardware signal quality, maybe you can adjust your input source to reduce the frequency and try.
thank you very much，This is very useful。
according to this document: https://community.nxp.com/docs/DOC-332679
the CSI Configuration that I have configured
but it still not work
Is there any problem with software configuration or FPGA vdeio source?