Audio MCLK out of GPIO_0 on i.MX6

[mmovsisyan]

Hello,

Measuring the MCLK driven by i.MX6 Solo out of GPIO_0 (muxed as CCM_CLKO1) reveals very poor clock quality. Although the NVCC_GPIO rail is at 3.3V, the MCLK only reaches 2V maximum and resembles more a triangular wave. 

The register value of IOMUX_SW_PAD_CTL_PAD (address 0x20E05DC) is 0x130B0. 

For comparison, both BCLK and LRCLK are nominal at 3.3V as expected and are square waveforms. 

Please advise. Must register settings be changed? Perhaps the GPIO_0 can't drive hard enough?

Thank you,

Mikael

[igorpadykov · Accepted solution]

Hi Mikael

yes reason may be insufficient drive strength/high capacitive load or very high

output frequency. Value " 0x130B0" corresponds to IOMUXC_SW_PAD_CTL_PAD_GPIO00

described in sect.37.4.371 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO00)

i.MX 6Solo/6DualLite Applications Processor Reference Manual

and one can try to set to max. values DSE, SPEED, SRE parameters.

May be recommended to use additional buffer as in i.MX6Q Sabre SD schematic spf-27392 p.8

Design files, including hardware schematics, Gerbers, and OrCAD files for i.MX 6Quad (i.MX 6Dual emu...

Best regards
igor