Are the i.MX6 GPIOs fail safe?

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Are the i.MX6 GPIOs fail safe?

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m_c
Senior Contributor I

For example, are they hi-Z when i.MX6 is powered off?  If I had a 10KΩ pull-up to 3.3V on one of the i.MX6 GPIO pins, would I expect the pin to stay high when the i.MX6 is powered off?  It’ll depend on the I_OFF leakage on the pin or the ESD structure.

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Yuri
NXP Employee
NXP Employee

Hello,

  Please use the Datasheet(s) to know pin states just after reset.

For example, Table 100 (21 x 21 mm Functional Contact Assignments)

of  IMX6SDLCEC  (Rev. 4, 12/2014) provides such information.

Also, please pay attention on Table 101 (Signals with Differing Before

Reset and After Reset States).

  Note, during power up sequence and short period of stabilization,

pin states are not defined.


Have a great day,
Yuri

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1,828 次查看
Yuri
NXP Employee
NXP Employee

Hello,

  Please use the Datasheet(s) to know pin states just after reset.

For example, Table 100 (21 x 21 mm Functional Contact Assignments)

of  IMX6SDLCEC  (Rev. 4, 12/2014) provides such information.

Also, please pay attention on Table 101 (Signals with Differing Before

Reset and After Reset States).

  Note, during power up sequence and short period of stabilization,

pin states are not defined.


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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m_c
Senior Contributor I

Customer want to know what the pin state is when the entire device is powered off.  Or more specifically what is the leakage current of the GPIO pins when the device is powered off.

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