Hi community,
I'm trying to write a new device driver for a camera sensor with MIPI interface connected to iMX6 Quad processor. The sensor has a parallel output data bus that comes into an FPGA that converts parallel data to Mipi serial data.
Has anyone some experience with Low Power signals in mipi?
On TX side, actually, I don't have LP management so I connected clk and data line to gnd by 50ohm resistor following FPGA data sheet for "free run" mode.
Do you know if it's possible to configure iMX6 MIPI CSI-2 in this way? Or CSI-2 needs the LP (Low Power) management with LP11 --> LP01 --> LP00 sequence?
Following some details:
Sensor: Aptina ar0134, 1280x960pix, monocrome 12bit, 54fps
FGPA: Lattice MachXO2 with MIPI CSI-2 Transmit Bridge IP Core
MIPI configuration: 4lane, freeRun (no LP signals management)
Linux driver: ov5640_mipi adapted in I2C configuration, data lane (from 2 to 4) and clock frequency.
Actually sensor is correctly probed and /dev/video0 device is created.
When I try to "cat /dev/video0" this is the consolle output:
root@xxxxx-imx6q:~# cat /dev/video0
clock_curr=mclk=27000000
ar0134_set_virtual_channel: virtual channel=0
mipi csi2 can not receive sensor clk! 200
ERROR: v4l2 capture: mxc_v4l_read timeout counter 0
cat: /dev/video0: Timer expired
power_down_callback: ipu0/csi0
Many thanks in advance for your support.
Bye.
Hi Igor,
with some manual wiring, I connected LP signals from TX side properly. I don't have all the necessary I/O, so I must reduce data lanes from 4 to 2.
After doing that, my driver has taken a step forward: now I no longer have the previous error (mipi csi2 can not receive sensor clk! 200).
Now I have another error:
ERROR: v4l2 capture: mxc_v4l_read timeout counter 0
These are the CSI registers when the timeout error appears:
MIPI_CSI_PHY_STATE: 0x300
MIPI_CSI_ERR1: 0x3
MIPI_CSI_ERR2: 0x0
Is 0x300 a good value for PHY state?
In the RM, about MIPI_CSI_ERR1, I found that the problem is "Start of transmission error on data lane x (no syncronization achieved)"
What exactly does it mean?
Thank You.
Hi Omar
I think you can look below
https://community.freescale.com/message/328301#328301
and create new thread
Thanks!
~igor
Hi Omar
there are no external signals "Low Power signals" in MIPI interface-
these are internal states of MIPI state machine.
Also there is no need for additional configuration in Linux driver
for this LP management.
Best regards
igor
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Many thanks for your answer Igor,
So, if I understood well, there isn't the possibility to configure the MIPI receiver (iMX6 CSI in this case) to work with a transmitter that produce or not LP signals. But does it mean that the transmitter MUST produce LP signals for an appropriate exchange between iMX6 MIPI internal states?
If this is the case... I'm wrong with my design!!
In may case, the sensor has a parallel bus and the parallel to MIPI conversion is made by an FPGA. FPGA has 4 and not only 2 output for clock/data:
- 2 differential output for HS (High speed) transmission
- 2 single ended (1.2V) signals to connect by two external 50ohm resistor to clk/data p and clk/data n respectively.
For a MIPI bus with 4data lanes there are a total of 20 I/O:
- clk: clk HS p, clk HS n, clk LP p, clk LP n
- data0: data0 HS p, data0 HS n, data0 LP p, data0 LP n
- data1: data1 HS p, data1 HS n, data1 LP p, data1 LP n
- data2: data2 HS p, data2 HS n, data2 LP p, data2 LP n
- data3: data3 HS p, data3 HS n, data3 LP p, data3 LP n
When I made the design, I want to be honest, really I didn't understand nothing about what LP signals do. So I preferred to make an easier connetion where the two single ended output are not used and the two 50ohm resistor are connected both to ground. In this case, when the internal FPGA logic put the differential output in three-state, both lines (p and n) are tied together to low. With this configuration there isn't the possibility to put line to hi level (LP11 state) and after lo low level (LP01 and LP00) before an HS transmission.
I don't know what kind of MIPI receiver can work properly in this way but what I'm understanding now is that iMX6 MIPI interface CAN'T run without properly management of LP signals from TX side.
Before going to change my board :smileysad:... could you confirm, please, that there aren't any low level registers that I can change to "say" to iMX6 MIPI interface that during LP state both differential lines for clk/data will be always to 00 state?
Many many thanks.
Hi, OmarPighi
How did you finalize the problem. I think, I have similar problem on IMX8mm + lattice. Did you added LP lines?
Thanks
Hi Omar
I think you should look at MIPI specification and
make signas according to its specs. Suggest to post
questions to MIPI forum
http://mipi.org/specifications/camera-interface
Best regards
igor
Ok, thank you very much for your suggestion.
Best regards,
Omar.